The Cores are Coming!
Humanoido
Posts: 5,770
http://www.wired.com/gadgetlab/2009/10/tilera-100-cores/
I think future props will break the 8-Cog barrier. Even if speed is down, there's a considerable power to having numerous clustered processors operating in unison. Maybe we won't see more cores in the next prop, but the one after will be a monster of a chip!
It is interesting that a plateau is reached in microprocessor speed and the next level of evolution is going to multi-processors.
We are beginning to see some of the power of multiple cores. Eight cores can do fantastic things. Just wait until they morph into 800 or more.
Humanoido
I think future props will break the 8-Cog barrier. Even if speed is down, there's a considerable power to having numerous clustered processors operating in unison. Maybe we won't see more cores in the next prop, but the one after will be a monster of a chip!
It is interesting that a plateau is reached in microprocessor speed and the next level of evolution is going to multi-processors.
We are beginning to see some of the power of multiple cores. Eight cores can do fantastic things. Just wait until they morph into 800 or more.
Humanoido
Comments
Also interesting how all external ram has to go through one core though
I wonder if they'll have a go at taking on nVidia using it in a graphics card, to do Ray casting, as it's not locked to drawing polys.
So the ultimate test of these fringe devices, is how well they run real software.
The problem will be heat and having to cool the chip. The other problem will be die size. Imagine producing die and one of the cores doesn't work. If too many of the chips are half defective then the problem becomes an economic issue.
It isn't an area where I specialize in so I can't tell you how to handle it or if chip makers will find it affordable. The other problem will be they will be marketing it towards the high end range for computers which will be expensive so that will leave most hobbyists out.
Not familiar with NUMA architectures then?
Also, have a look at the architecture used in the late AMD processors, where the memory controller sits on a high speed internal bus as a peer to the cores.
This is an area where the Propeller doesn't scale very well. The more cogs you add, the longer each waits for hub access.
Multitasking is probably the better word for what the prop can do. Multitasking is sometimes better than single tasking. Imagine if you wanted to run Microsoft Word, Excell and another program but kept having to close one to run the other. You would be wasting your time closing and loading programs.
So the cog is 4x faster (1 instruction per clock) and 2x faster (clock).
On top of this there is the block transfer instruction that will shift a lot of memory at 4x32bits from/to hub.
The Prop II is touted to have extra fifo memory per cog - 256 or 512 longs???
Two things I advocated was more cogs and a mechanism to allow cogs additional accesses to hub on a priority basis. So you could have 1 cog getting 4x access and the other cogs getting reduced access unless the priority cog did not require it (kills determinism though).
Another suggestion was to allow each cog to pair up with an adjacent cog and take all its resources, meaning bank switching the extra 512 longs of code space, and it's hub access cycle.
We may see these things on Prop III. Remember, this is not targetting an Intel/Atom or other high powered PC/Laptop/iPad replacement chip.
There are many ways to cool a chip. Small Peltier devices, like tiny electric refrigerators, have been used for decades in astronomical CCD imaging sensors for supercooling to -107 deg. F. The technology is available for multiple core chips when needed.
Dies can be produced with "extra quantity" of computers available to compensate for defective ones. A chip rated for 100 cores, cast with 110, can have 10% defectives voided and still perform to specs.
New technology often starts out at a premium, but with competition and demand, the price will go down.
High end technology, and sometimes rather quickly, filters down in cost and availability. The hobbyists will have an exciting future with these new multiple core devices.
Humanoido
With huge, bloated, OSs there becomes a necessity for one core to do software overheads such as virus scanning on a continious basis, one core to "phone home to the mothership" to check continiously that that program or content is really yours and if you can still be given permission to use it, even if it is. Then there is a core for .... and a core for ....
100 cores need to be fed and watered, and the the fruits or their labours gathered back in, that will occupy a few more.
I'm just an old cynic that is having to get a brain away from the "something else has to happen now, wheres that interupt?" way of thought.
The idea is to either be a clever programmer and avoid huge bloated OS' or with MCS, multiple core systems, that OS can be distributed from processor to processor.
Its possible that each core will handle the transfer of its information, and deliver the fruit at harvest time, so you don't need one core hand picking the entire garden and getting all worn out.
Humanoido