Reset pin as output
ManAtWork
Posts: 2,178
The propeller data sheet says...
However, it is a bit unclear what condition will actually drive RESn low if it is used as output with BOEn=low. I tried out the demo board and I notice that RESn is driven low whenever VDD is <3V. Can I assume that RESn is also driven low at power up if VDD rises slowly enough, say, at a rate of <1V/ms?
I have a design with a propeller and an FPGA. I want to make sure that the FPGA is also reset any time the propeller is reset so both stay synchronized. I cannot do this with a programmed IO pin because it the bootloading process from EEPROM takes too long and would leave the FPGA in an undefined state.
If the brown out detector doesn't drive RESn low reliably or if power up reset is not guaranteed I would have to use an external reset generator to reset both propeller and FPGA, something I'd like to avoid if possible.
Thanks
BOEn
Brown Out Enable (active low). Must be connected to either VDD or VSS. If low, RESn becomes a weak output (delivering VDD through 5 kΩ) for monitoring purposes but can still be driven low to cause reset. If high, RESn is CMOS input with Schmitt Trigger.
RESn
Reset (active low). When low, resets the Propeller chip: all cogs disabled and I/O pins floating. Propeller restarts 50 ms after RESn transitions from low to high.
However, it is a bit unclear what condition will actually drive RESn low if it is used as output with BOEn=low. I tried out the demo board and I notice that RESn is driven low whenever VDD is <3V. Can I assume that RESn is also driven low at power up if VDD rises slowly enough, say, at a rate of <1V/ms?
I have a design with a propeller and an FPGA. I want to make sure that the FPGA is also reset any time the propeller is reset so both stay synchronized. I cannot do this with a programmed IO pin because it the bootloading process from EEPROM takes too long and would leave the FPGA in an undefined state.
If the brown out detector doesn't drive RESn low reliably or if power up reset is not guaranteed I would have to use an external reset generator to reset both propeller and FPGA, something I'd like to avoid if possible.
Thanks
Comments
-Phil
I just took this picture:
Trace #1 is the reset signal, trace #2 is VDD(3.3V) at power up of the demo board. Reset stays low until VDD reaches about 2.9V.
Please don't misunderstand me. I don't wan't to say that you're wrong and I know that my spot check proves nothing. I'd just like to know who to trust more. Do you have your information out of some document from parallax or is it just experience?
Thank you very much
-Phil