I wouldn't use a 74HC573 for the latch. The setup and propagation delay times are horrible under 4.5V VCC, and the 2V VCC numbers would probably never work. I've used 74LVC573 and 74LVT573 ... the LVC family has wonderful AC parametrics.
You should probably go through the driver and put in NOPs between address set and latch instructions. Use 2 NOPs just to be safe, then tune it later. I would do this for you, but I have a massive headache today. Sorry.
Another consideration is to try Ding-batty's driver since it is more conservative with refresh. I don't think anything will work reliably with the 74HC573 until you insert those NOPs, but it would be good to try the Ding-batty's driver first just to get a baseline (working or not).
The one thing that should fail is testing beyond 32MB. The test I posted does not attempt to auto-detect beyond 32MB, so that's one issue. The other issue is the address bit (A11 ???) has to be set up correctly for the 64MB part - I'm sure that's not being done.
I will try and get holds of a LVT version of the latch. The failure is before the 16MB bank junction so I though about experimenting with shifting down the addr pins to see if I could at least get 4 banks of 8MB, but then I remembered whilst driving into work today that the chip has to receive its initialization bits and bobs, so a stare at the data sheets is required.
My poor old 20MHz 'scope couldn't keep up with the refresh bursts, on the CLK line, they show up as a series of half amplitude sine waves.
I pushed the Prop's clock down to 40MHz just to see if the problem was the speed of the latch. the tests still failed at 16MBs. As the tests seem to fail at other addresses than the 16MB bank boundries I could try the cludge of trying to force the chip into thinking it's a smaller 32MB one by forcing the upper addr pins to zero, the spec allows for this (I think).
I think that rather than wantantly craving for the whole nine yards, this SDRAM is from a DIMM that was on its way to the skip (removed, carefully, by an electric paint stripper (the parafin blowlamp wouldn't start)), I could try a reality check in putting a real large program into the beasty an seeing if the 8MB+ is truely usable. I get bored typing in 8KB of code, so all of this is an exercise in hardware harvesting. I still want to get rid of those latches on the DracBlades, this is two less (one to go).
I pushed the Prop's clock down to 40MHz just to see if the problem was the speed of the latch.
Taking that approach, you need to drop it to 20MHz.
RE: EDO-DRAM. A recent driver is posted in the VMCOG thread. The driver requires a latch.
RE: Getting rid of latches. I'm taking a totally different approach these days.
Rayman and I discovered this Quad bit 8 pin Flash recently at about the same time - SQI is one acronym. I've been furiously pursuing this path ever since then with SpinSocket-Flash, PropTouch, and PalmProp.
Using 2 SQI chips in parallel for an 8 bit bus, only 10 pins are necessary and the read access will be as fast as SDRAM. Of course since it's Flash, you can't use it like an SRAM or SDRAM, but I've found that using external memory for things like stack and global data makes performance suffer a bit too much anyway.
What are advantages of using SQI Flash?
Fast startup - no need to load big programs at every boot.
Non-volatile storage for sleep mode programs.
Fast, 10 pin program storage.
Small footprint.
High density: 1MB PDIP, 2MB SOIC8, and 16MB WSON available.
Drivers are known to work.
Fast access with 5MB/s (80MHz) read and program.
Cheap!
What are disadvantages of using Flash in general?
Bit cells limited by specification to around 100K program cycles.
Wear-leveling is required for file-system use.
Not intended to be used like RAM.
Requires programming in sectors. No per byte access.
I doubt that Flash will be usable on emulations, but I've never studied that so I'm just guessing.
My next software thing after writing a usable PropTouch LCD is a Catalina port for SQI FlashCache.
Once the SQI FlashCache is ported, I'll go ahead and port the SDRAMcache too.
20MHz ???? I was falling asleep with it set to half !!!!
I did toy with that but worried over the consequences on the refresh side (and the 115200 Baud spat it out). I am on 15 hour days at the moment so thinking is going to happen until Thurs/Fri. I did get it to pass the psudo addr test up to 13MB (using s d00000) before sleep became important.
The old DRAMs had real latches built in on the RAS and CAS feeds (I think) and some of the EDOs could suffer a bit of that too, it's just my fixation to get rid of as much as possible. There is the disadvantage the to get back some pins I end up using 4053s for the KBD etc. I know that I could use the single pin KBD and video objects but the only small video monitor I have is so old that the focus is shot and so I tend to use VGA, even if it is 640x480 white on blue.
Come the glorious day, when the Prop2 pops up, all these worries will be but distant memories ....(until bigger and more ridiculous projects are slung at it)
Comments
Here is a link to a 74LVC573 PDIP
You should probably go through the driver and put in NOPs between address set and latch instructions. Use 2 NOPs just to be safe, then tune it later. I would do this for you, but I have a massive headache today. Sorry.
Another consideration is to try Ding-batty's driver since it is more conservative with refresh. I don't think anything will work reliably with the 74HC573 until you insert those NOPs, but it would be good to try the Ding-batty's driver first just to get a baseline (working or not).
The one thing that should fail is testing beyond 32MB. The test I posted does not attempt to auto-detect beyond 32MB, so that's one issue. The other issue is the address bit (A11 ???) has to be set up correctly for the 64MB part - I'm sure that's not being done.
Thanks for all your help and these tips.
I will try and get holds of a LVT version of the latch. The failure is before the 16MB bank junction so I though about experimenting with shifting down the addr pins to see if I could at least get 4 banks of 8MB, but then I remembered whilst driving into work today that the chip has to receive its initialization bits and bobs, so a stare at the data sheets is required.
My poor old 20MHz 'scope couldn't keep up with the refresh bursts, on the CLK line, they show up as a series of half amplitude sine waves.
I hope that your headache has gone away.
addit
About a third of the way down this
http://forums.parallaxinc.com/forums/default.aspx?f=25&p=1&m=473459
you said you had some EDO code, do you still have access to it?
I think that rather than wantantly craving for the whole nine yards, this SDRAM is from a DIMM that was on its way to the skip (removed, carefully, by an electric paint stripper (the parafin blowlamp wouldn't start)), I could try a reality check in putting a real large program into the beasty an seeing if the 8MB+ is truely usable. I get bored typing in 8KB of code, so all of this is an exercise in hardware harvesting. I still want to get rid of those latches on the DracBlades, this is two less (one to go).
Thanks for all the patience.
RE: EDO-DRAM. A recent driver is posted in the VMCOG thread. The driver requires a latch.
RE: Getting rid of latches. I'm taking a totally different approach these days.
Rayman and I discovered this Quad bit 8 pin Flash recently at about the same time - SQI is one acronym. I've been furiously pursuing this path ever since then with SpinSocket-Flash, PropTouch, and PalmProp.
Using 2 SQI chips in parallel for an 8 bit bus, only 10 pins are necessary and the read access will be as fast as SDRAM. Of course since it's Flash, you can't use it like an SRAM or SDRAM, but I've found that using external memory for things like stack and global data makes performance suffer a bit too much anyway.
What are advantages of using SQI Flash?
- Fast startup - no need to load big programs at every boot.
- Non-volatile storage for sleep mode programs.
- Fast, 10 pin program storage.
- Small footprint.
- High density: 1MB PDIP, 2MB SOIC8, and 16MB WSON available.
- Drivers are known to work.
- Fast access with 5MB/s (80MHz) read and program.
- Cheap!
What are disadvantages of using Flash in general?I doubt that Flash will be usable on emulations, but I've never studied that so I'm just guessing.
My next software thing after writing a usable PropTouch LCD is a Catalina port for SQI FlashCache.
Once the SQI FlashCache is ported, I'll go ahead and port the SDRAMcache too.
I did toy with that but worried over the consequences on the refresh side (and the 115200 Baud spat it out). I am on 15 hour days at the moment so thinking is going to happen until Thurs/Fri. I did get it to pass the psudo addr test up to 13MB (using s d00000) before sleep became important.
The old DRAMs had real latches built in on the RAS and CAS feeds (I think) and some of the EDOs could suffer a bit of that too, it's just my fixation to get rid of as much as possible. There is the disadvantage the to get back some pins I end up using 4053s for the KBD etc. I know that I could use the single pin KBD and video objects but the only small video monitor I have is so old that the focus is shot and so I tend to use VGA, even if it is 640x480 white on blue.
Come the glorious day, when the Prop2 pops up, all these worries will be but distant memories ....(until bigger and more ridiculous projects are slung at it)