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A few questions about TMS417400A DRAM — Parallax Forums

A few questions about TMS417400A DRAM

Jorge PJorge P Posts: 385
edited 2010-07-21 09:38 in Propeller 1
I have a few TMS417400A IC's I scrapped from some old PC memory.· The datasheet says
The TMS41x400A is a set of 16 777 216-bit dynamic random-access memory (DRAMs) devices organized as 4194304 words of 4 bits each. The TMS41x400A employs state-of-the-art technology for high performance, reliability, and low power.
These devices feature maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS416400A and TMS417400A are offered in a 24/26-lead plastic surface-mount SOJ package (DJ suffix). This package is designed for operation from 0°C to 70°C.
Mine is the one with the DJ suffix and 60-ns.··Wouldn't that mean·16,777,216 bits = 2,097,152 bytes making this a 2Mb chip? or did I do that wrong?

I only want to access 512K Bytes of the chip, can I limit the amount of address/data pins I connect to the prop or do I have to connect all the pins of this DRAM Chip?

Since I want to use only 1/4 of the memory, wouldn't I only need 1/4 of the address lines?

thanks in advance.

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Comments

  • LeonLeon Posts: 7,620
    edited 2010-07-21 05:44
    You will need two of them for a 2 Mbyte byte-wide memory.

    You do know that you will need to provide some means of refreshing them? It can add quite a lot of complexity, unless you use software refresh.

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    Leon Heller
    Amateur radio callsign: G1HSM

    Post Edited (Leon) : 7/21/2010 5:58:39 AM GMT
  • Jorge PJorge P Posts: 385
    edited 2010-07-21 06:03
    Yes I am considering what the datasheet says about that
    Datasheet said...
    TMS417400A
    A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing each of the 2 048 rows (A0–A10). A normal read- or write cycle refreshes all bits in each row that is selected.
    A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh.
    hidden refresh
    Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally.
    CAS-before-RAS (CBR) refresh
    CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The external address is ignored, and the refresh address is generated internally.

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  • LeonLeon Posts: 7,620
    edited 2010-07-21 06:10
    I'd be inclined to devote a cog to that, and use software refresh.

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    Leon Heller
    Amateur radio callsign: G1HSM
  • heaterheater Posts: 3,370
    edited 2010-07-21 06:23
    I'd be inclined to forget the whole idea. If you only need 512K there are other easier solutions that won't require an extra Cog.

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  • LeonLeon Posts: 7,620
    edited 2010-07-21 06:34
    It probably is a waste of time, unless he just likes playing with stuff like that.

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    Amateur radio callsign: G1HSM
  • Toby SeckshundToby Seckshund Posts: 2,027
    edited 2010-07-21 07:19
    I was starting on this path about 6 months back. First I wondered about SDRAM, but got a bit lost and then scounged some EDO DRAMs, off of an old DIMM. I even shuffled up the pins on a DracBlade(ish) to get more more available for the job. I then got a new job that leaves me with far less free time and I started to listen to all the others that pointed out that it was a lot of trouble, for little return.

    I was just thinking along the lines of, the DracBlade uses a bunch of latches and a lot of that is inbuilt to the DRAMs.

    Have you seen, http://www.myplace.nu/avr/dram/index.htm·which is simular to the sort of thing (just with one of those "other" chip thingies).




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    Why did I think a new, more challenging, job was a good idea ??

    Post Edited (Toby Seckshund) : 7/21/2010 7:25:30 AM GMT
  • Jorge PJorge P Posts: 385
    edited 2010-07-21 09:22
    @Leon

    Yes, I am just bored and playing around with the idea. It is something I found in my parts bin I just dug out of storrage.

    EDIT: I am trying to not use all the address lines....

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  • AntoineDoinelAntoineDoinel Posts: 312
    edited 2010-07-21 09:38
    Jorge

    The problem with multiplexed addresses is that every address line you leave out, it will divide the available space by FOUR, not just two.

    So in the end you just spare ONE pin to get from 4Mx4 (2MB) to 1Mx4 (512KB).

    However if the chips are not mounted on a module, then you have control of the output enable pin (not fixed to low like on SIMMs), and you MIGHT be able to combine data and addresses, like the example in the link that Toby suggested.

    Alessandro

    Post Edited (AntoineDoinel) : 7/21/2010 9:44:48 AM GMT
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