Using the Propeller as a clock generator

Larry C.

I'm working on a project that will use a digital frequency synthesizer (DDS) chip. I plan to derive the master clock for the DDS from the Propeller counter - probably in the 0.5 to 2 MHz region.

I'd like this clock as stable and jitter-free as possible, which leads to two questions:

1) Am I correct in assuming that some division ratios of the Propeller clock are cleaner than others? Like, for instance, clkfreq / 2^n

2) Alternatively, is there any drawback to tapping a signal off of pin XO (P29) of the Prop chip directly? (Through a CMOS buffer. If there's a slight change in xtal frequency due to buffer input capacitance, it won't matter, as long as it's stable.)

Thanks for any insights,

Phil Pilgrim (PhiPi)

1) Absolutely do use clkfreq / 2^n. Anything else will get you major jitter.

2) I'd be inclined to avoid messing with XO. Use a counter output instead.

Also, be aware that the DDS, like the Prop, uses an NCO and will introduce its own jitter, albeit not nearly as much as the Prop, since sine waves have "softer" edges.

Here are a couple of my own threads on the subject:

http://forums.parallax.com/showthread.php?p=912712
http://forums.parallax.com/showthread.php?p=921101

Calming the jitters is something that I'm very actively pursuing at the moment. I've also bought a DDS chip but have not tried it yet.

-Phil

Post Edited (Phil Pilgrim (PhiPi)) : 7/14/2010 6:48:24 PM GMT

Larry C.

Thanks for the pointers. And, yes, I am very aware of the phase noise problem with a bare DDS synthesizer. I was thinking of using a PLL to clean it up ( '4046, maybe?), so I'll be perusing your previous threads with interest.

Some years ago, I and one of my co-workers collaborated on an investigation of noise in a DDS, and we published a paper on the subject. I don't have a copy of it, but if you're interested, I can probably find out where you could obtain one.

- LC -

Phil Pilgrim (PhiPi)

Thanks, Larry. Yes, I'd be very interested in seeing that paper.

-Phil

tdlivings

Larry
·In my AD9833 DDS experiments I used a cog counter to generate the reference clocks and when I did not have a power of two in the freq control field, a 25MHZ setting , I had much more jitter than when I used 2^28 for the control value and generated 20MHZ for the clock. The best way to put it other than visual on the scope was to say it was a task to get the scope trigger to lock on without a power of two in the control field.
AD9833 discussed here http://forums.parallax.com/showthread.php?p=891299

Phil
·AD9833 will not do 14MHZ but here is an interesting link with some videos. I found it just looking for DDS info on the net. DDS60 board looks interesting. You have to go to the bottom of page then home to get to main page.
http://midnightdesignsolutions.com/HC908VFO/index.html

Tom
·

Leon

DDS chips are generally very good in terms of phase noise, but always have spurs. A PLL is sometimes used to clean up the spurs rather than the phase noise. The spurs can often be avoided by good design in narrow-band systems, but can cause problems in wide-band applications.

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Leon Heller
Amateur radio callsign: G1HSM