16-bits is quite adequate for their intended purpose. They are often used in connection with the capture of external events, see the portXS1.pdf document on the XMOS web site for details.
There are also 10 32-bit counters for each core, used as high-resolution timers. PWM can easily be implemented with a minimal amount of code.
XMOS uses HW threads, not SW, switched in one clock (400 MHz). 100 MHz events can be captured.
XMOS uses HW threads, not SW, switched in one clock (400 MHz). 100 MHz events can be captured.
I can see they can sample serially at 100MHz, but to then derive Frequency information from a sampled stream, you need software - and that puts limits on the usable Frequency, as the SW has to keep up with the streaming samples.
I see an example here that claims 40MHz for a PROP Frequency counter, which is faster than any XMOS Port+SW solution, but still rather lower than a hardware counter is capable of.
Ideally, I am looking for a device that does NOT constrain the timing by forcing a layer of software into what should be a simple hardware task.
Comments
There are also 10 32-bit counters for each core, used as high-resolution timers. PWM can easily be implemented with a minimal amount of code.
XMOS uses HW threads, not SW, switched in one clock (400 MHz). 100 MHz events can be captured.
I can see they can sample serially at 100MHz, but to then derive Frequency information from a sampled stream, you need software - and that puts limits on the usable Frequency, as the SW has to keep up with the streaming samples.
I see an example here that claims 40MHz for a PROP Frequency counter, which is faster than any XMOS Port+SW solution, but still rather lower than a hardware counter is capable of.
Ideally, I am looking for a device that does NOT constrain the timing by forcing a layer of software into what should be a simple hardware task.