Structure of @rx_head in FullDuplexSerialPlus
ke4pjw
Posts: 1,173
I need to receive data with the prop via serial => 512kbps and find that spin appears to top out at about 115.2kbps. I want to rewrite my code in PASM, but understanding FullDuplexSerialPlus has me scratching my head a bit. It looks like all of the intercog communication happens through @rx_head. (But I could be way off here)
Does anyone know the structure of @rx_head in FullDuplexSerialPlus? Or maybe point me to a tutorial on FullDuplexSerialPlus that will explain it to me like I was a 4year old [noparse];)[/noparse]
Thanks in advance.
--Terry
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-- Terry
Does anyone know the structure of @rx_head in FullDuplexSerialPlus? Or maybe point me to a tutorial on FullDuplexSerialPlus that will explain it to me like I was a 4year old [noparse];)[/noparse]
Thanks in advance.
--Terry
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-- Terry
Comments
There are head and tail pointers into the buffer which is 16 bytes long.
The system works like this. Both the head and tail pointer start off at zero equal to each other. When a byte comes in off the serial line the byte is put into the serial buffer like this "buffer[noparse][[/noparse]headIndex] := byteOffSerialLine" Then the head pointer (which is actual and index in the serial buffer - it goes from 0 to 15) is incremented and then anded wtih $F to make sure it nevers gets above 15.
When the spin code then wants to get a byte from the serial buffer it grabs the byte pointed to by the tail index in the serial buffer and then increments the tail pointer by 1 and ANDs it with $F.
So, by doing this you have a First In First Out (FIFO) buffer in which the head and tail pointer tell you where valid data is and isn't.
The amount of stuff in the FIFO buffer is equal to ((head - tail) & $F). So this means the buffer can hold 15 bytes or space at maximum and when the head and tail pointer are equal to each other at any point the buffer is empty.
I hope this helps. "Google circular FIFO buffer otherwise"
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Nyamekye,
This loop took·about 80 usec per byte, which is 125 kbps.· It would have been slightly faster if I used pdata[noparse][[/noparse]j] := i instead of doing this in two lines.· However, it wouldn't have achieved 512 kbps.· There is a significant amount of overhead in calling ser.rx.· You might be able to achieve 512 kbps if you create a block read function in FDS+ as follows:
This method will copy up to "num" bytes from the RX serial buffer to the buffer pointed to by "ptr".· It will return the number of bytes transferred.· If I get a chance I'll run a timing test on this to see how fast it is.
Dave
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-- Terry
Dave
·Edit: I forgot to update rx_tail.· I added the necessary line above.
Post Edited (Dave Hein) : 6/19/2010 11:20:30 PM GMT
Dave
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I have now figured out how and why the pointer that is passed off to the cog running the UART interfaces with the locations in hub memory. I have written some PASM to pull a byte from the buffer and compare it with the ASCII value of the capitol letter "D". It runs in a separate cog from the UART, though the pointer to rx_head is passed to this code.
The code works 100% up to 250kbps. Does not decode at 460.8kbps or 921.6kbps. It will decode properly about 10% of the time at 1Mbps. Since I am only sending one character at a time, by hand, I do not believe this to be a buffer over run issue. I suspect that either I have a hardware issue (RF needs to be decoupled or standing waves on the transmission line) or I am running against the limits of a cog's processing power that is running FullDuplexSerialPlus. I am thinking of removing the ping-pong multitasking and separating the UART into two cogs. One for RX and one for TX. I do have some doubt if this is a software issue, as Dave was able to reliably receive data at 1Mbps.
I am not sure what direction to head to next. Hardware or software.
Thanks guys!
--Terry
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-- Terry
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-- Terry