[resolved][puzzle] 33% setup

kuroneko

Not particularly difficult but I share it anyway. You have space for a single PASM instruction left and you need half the clock frequency on pin 0 (e.g. 40MHz on a 80MHz setup). The pin is already an output (that's when you ran out of space). How?

Don't spoil it for others in the first reply [noparse]:)[/noparse]

Post Edited (kuroneko) : 4/21/2010 7:23:30 AM GMT

Phil Pilgrim (PhiPi)

So, ... what? I'm supposed to post a wrong reply first?

Seriously, that's a great brain twister! To do this with a counter, you have to write two destinations, ctra and frqa. But one instruction can't do that by itself. So it's going to involve co-opting another, extant instruction in weird, unnatural ways. Hmm.

-Phil

Mike Green

If you use either a positive edge or negative edge detector mode with feedback, you can set both the counter mode and the PLL divisor with one MOVI instruction with an immediate operand. The PLL divisor isn't used. The A pin (and B pin) will be zeroed when the cog is reset, so the instruction would be:

MOVI CTRA,#%0_01001_000

Pin zero will be toggled every clock cycle, so the frequency seen on pin zero will be CLKFREQ/2.

Note that this scheme can be used for other pins if you have a 2nd long available for the pin numbers (and the mode)

Post Edited (Mike Green) : 4/19/2010 4:43:14 AM GMT

Phil Pilgrim (PhiPi)

Good one, Mike! I'd forgotten about the feedback modes.

-Phil