Metastability

K2

As a result of a paper I read years ago, I've been on edge regarding metastability (no pun intended). Sometimes it amazes me that computers work at all.

Suppose one were to devote a cog to reading the current state of a pin several million times a second. Suppose further that the pin in question is driven by an external asynchronous signal that changes state approximately every microsecond. (I'm describing essentially a high speed counter application.)

Over time, the chances that the external signal will change state at the very same instant that the pin is sampled by the cog, is very high. Is the VLSI process in which the Propeller was implemented designed to handle this gracefully? Is there any guarantee against a protracted metastable state that would result in inaccurate sampling?

I'm seeking some sort of warm fuzzy before proceeding with a particular application.

Searider

I guess you could introduce a very short random delay to your sampling loop so that it would have a much lower chance of falling into sync with a source signal.

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Searider

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pacman

In my industry the "rule of thumb" is _always_ sample at _at least_ "twice+" the input frequency.

Device frequency = 10 kHz, Sample at better than 20 kHz

Though if you were running in a dedicated cog flat out how you would combat that (without going to an external high speed counter chip) is a mystery to me....

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Peter Jakacki

Metastability is like betting both ways, you will get one or the other, what's the problem? It's not strictly an error when it comes to sampling inputs as either state read is or was valid at that instant. If you are looking for a state "right on the edge" then either you just missed it or you just got it. Can you actually demonstrate a "real" example where metastable conditions pose a problem?

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*Peter*

Mike Green

It is always possible in a clocked system (which the Propeller is) to sample a changing input signal during its transition from one stable state to another. The only way to deal with this sort of thing is to use an edge triggered flip flop to hold the 0 to 1 or 1 to 0 transition whenever it occurs until the Prop can sample it (and reset the flip flop). This still won't work if the signal keeps changing while the Prop is sampling it and resetting the flip flop. It's possible to build a hardware synchronizer that's faster (and a little more complicated) if you need it.

Peter Jakacki

Metastability is normally a problem to do with setup and hold times on flip-flops so by introducing a flip-flop you achieve nothing, at some point the setup and hold times may not be met. The only way a flip-flop will help is if you have the synchronous clock for the input data so that you can sample it when it is stable so the Prop would be able to asynchronously sample that latched data. If the input signal changed at the sample rate then this method may help but there are other ways of handling high-speed signals in this case as a serial in shift-register would be far more useful. Practically all input sampling is non-critical and oversampled anyway as in the case of sensing a change in input, if you just missed it then you get it next time etc.

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*Peter*

HollyMinkowski

If you read the state of the pin using more than one processor ...each processor taking a reading
very slightly out of time sync couldn't you track the pins changing state without worrying about taking
a reading just as the pin state changed?

One processor might take a reading just as the state changed but there would be no way all
of the processors could as they each would read at slightly different times.

It would be kind of like looking at an analog recording of the pin changes instead of a purely binary
recording from a single source. You could figure out from the multiple readings that were taken
just exactly how the pin is being set... I can't see how this scheme would ever give a false read.

Does that make any sense?

Peter Jakacki

HollyMinkowski said...
If you read the state of the pin using more than one processor ...each processor taking a reading
very slightly out of time sync couldn't you track the pins changing state without worrying about taking
a reading just as the pin state changed?

One processor might take a reading just as the state changed but there would be no way all
of the processors could as they each would read at slightly different times.

It would be kind of like looking at an analog recording of the pin changes instead of a purely binary
recording from a single source. You could figure out from the multiple readings that were taken
just exactly how the pin is being set... I can't see how this scheme would ever give a false read.

Does that make any sense?

That's just a way of oversampling the input state but once again, it doesn't make any difference. Metastability has been presented as a "problem" by the OP yet no evidence is furnished as to how this is or could be a problem with the Prop and the way it is used.

When actual digital logic circuits are designed then metastability/race conditions are always a consideration but this is also why practically all digital logic systems are clocked so as to synchronize the signals. So systems are actually slowed down to the lowest common speed.

I repeat "how is it a problem?" No, it isn't. So it's not a problem to be solved.

We get a lot of these types of perceived problems on the forum and I am always amazed at how because it has been labeled as such that people try to solve it without question. The problem is in perceiving it as a problem to be solved.

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*Peter*

Phil Pilgrim (PhiPi)

Some processors cascade D registers to limit (but not entirely eliminate) metastability issues on their inputs. (It's a statistical thing, after all.) But the downside is that each such register adds a one-clock delay to the final input sampling. AFAIK, the Propeller doesn't do any input synchronization. As I understand it, the pins are sampled directly during the source cycle of the instruction when INA is the source register.

-Phil

Dr_Acula

There could easily be fluctuations, eg the threshold point between high and low could be varying slightly with slight mains hum on the DC supply. Or at a higher frequency from a switching power supply. Ok worst case scenario, there is lots of noise at the transition point:
0000010000100101101011101111011111111111111111111111111111111

You can fix that with a latch in software - eg as soon as you get that first 1 you latch the state of a software flipflop that now cannot change state for a short period of time (short relative to the shortest pulse you expect to measure).

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www.smarthome.viviti.com/propeller

Tracy Allen

David, You might be reassured by Chip Gracey's comments on metastability in relation to design of the prop in this thread,
http://forums.parallax.com/showthread.php?p=632513
about halfway down the page. He verifies what Phil mentioned, that there is no synchronizer on the prop input, but neither is there the kind of fan-out directly from the inputs that could lead to missynch of internal states.

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Tracy Allen
www.emesystems.com

K2

Thanks for the great responses!

> You might be reassured by Chip Gracey's comments on metastability in relation to design of the prop in this thread,
> forums.parallax.com/forums/default.aspx?f=25&p=1&m=172375

Tracy, you and rokicki, back in 2007, articulated precisely what I was concerned about...oscillations that would result in an inaccurate (ie, high) count. Thank you very much for the link to this discussion.

While I appreciate Chip's point about the penny falling on the razor's edge, I'm not entirely certain that the metaphor (or analog) holds. I'll have to give the matter more thought. I still can't shake off my concerns...

Meanwhile, an external counter that is clocked by the signal in question wouldn't cost much and might pay off in peace-of-mind, if nothing else.

This may be a case where an actual test is in order. One trillion counts later I might find the peace-of-mind I seek.

Post Edited (David Jensen) : 3/25/2010 7:25:33 AM GMT