Propeller development HDL

Lord Steve

Does Chip Gracey use gate-level Verilog or RTL Verilog when designing the hardware description for the Props?· I am thinking about delving into my first FPGA project.

Thanks.
·

Leon

Both Xilinx and Altera offer VHDL and Verilog with their tools. I prefer VHDL. You can even mix them if you wish.

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Leon Heller
Amateur radio callsign: G1HSM

Post Edited (Leon) : 3/17/2010 7:52:04 PM GMT

Lord Steve

What I am asking is if Chip used gate-level building blocks to describe everything or if he used RTL bottom-to-top or just what he did, in general.

Leon

The Propeller was actually designed at the transistor level using schematic entry. They presumably used schematics for prototyping on the Stratix FPGAs they used.

I wouldn't follow their example, you'd be better off using VHDL or Verilog.

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Leon Heller
Amateur radio callsign: G1HSM

Post Edited (Leon) : 3/17/2010 8:20:55 PM GMT

Lord Steve

Ah, yes.· That does seem like over kill for me.· I was thinking it may have been at the gate/flip-flop level, which is what I think I may like to do.

Thanks.

RvnPhnx

Lord Steve,
If you aren't debugging at the wavefront timing level (which they probably had to do to perfect the prop design, not to mention that they didn't want to use anybody else's cell libraries and have to fork over cash for them) then just doing your work in 'beh' blocks should probably cut it to get started. Once you get past that then thinking more specifically about the RTL layout of things will be fruitful.

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--RvnPhnx