Question concerning the 74HC165 parallel-to-serial shift register...ANSWERED/CL

davejames

Hi All,

I'm a bit confused whether the 74HC165 parallel-to-serial shift register (Parallax #602-00010) requires "the first data bit ready before the first clock pulse (PRE) or after the first clock pulse (POST)".

I can't find anything written in the 165's data sheet, and the timing diagrams are so cluttered that my eyes imploded.

Anybody know?


Thanks much,

DJ

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Post Edited (davejames) : 3/6/2010 4:27:57 PM GMT

kf4ixm

it looks like the clock pulse is first, then the first data bit with the next clock pulse.

http://www.nxp.com/documents/data_sheet/74HC_HCT165.pdf

Chris Savage

DJ,

Example code for both the 74HC595 and the 74HC165 can be found on the Stamp Works product page. You can even download the manual for free and it completely explains the operation. I hope this helps. Take care.

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Chris Savage

Parallax Engineering
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Mike Green

The shift registers in the 74HC165 (like the 74HC595) are positive edge triggered. They shift when the clock pulse goes from low to high. Whether this is pre- or post- depends on the polarity of the clock pulse. If the resting state of the clock pulse is low, then it's triggered by the leading edge of the pulse. If the resting state of the clock pulse is high, then it's triggered by the trailing edge of the clock pulse. The data has to be stable prior to the low to high transition of the pulse.

davejames

All - thank you.

I'm calling this request closed.

DJ

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davejames

Hi All,

Utilized the Stamp Works example suggested by Mr. Savage, and, after wiring things correctly (duh!), I'm able to shift in 8 bits of data and display them in the debug window.

Woo-hoo!

DJ

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