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New Junctionless Transistor !! — Parallax Forums

New Junctionless Transistor !!

QuattroRS4QuattroRS4 Posts: 916
edited 2010-02-24 07:25 in General Discussion
Tyndall Ireland - breakthrough to revolutionise microchip manufacturing.

www.tyndall.ie/

More specifically..

www.tyndall.ie/control/include_database.html?DB=~/press.dbf&RO&OL&TC=1&DE=1

Just a heads up to Chip to keep this in mind for Prop3 !! (tongue in cheek !).


Regards,
John Twomey

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'Necessity is the mother of invention'

'Those who can, do.Those who can’t, teach.'
'Convince a man against his will, he's of the same opinion still.'

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Comments

  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2010-02-24 05:37
    The article said...
    Cork, 21 February 2010: A team of scientists at the Tyndall National Institute have designed and fabricated the world s first junctionless transistor that could revolutionise microchip manufacturing in the semiconductor industry.
    That's interesting. I thought all MOSFETs were "junctionless".

    -Phil
  • Beau SchwabeBeau Schwabe Posts: 6,568
    edited 2010-02-24 07:25
    Phil Pilgrim,

    There are vertical junctions formed in the CMOS design process that contribute to the parasitic BJT effect commonly referred to during "latch-up".

    Latch-up can be reduced greatly if the 'source' connection has a good well-tie to either the NWELL for PMOS transistors or PWELL(P-substrate) for NMOS transistors. Doing so lowers the N+/P+ resistance on the parasitic BJT's Emitter-Base junction. A lower resistance here makes it harder for the parasitic SCR to turn 'ON' and latch. (see attached image)


    ...That said, the circular transistor is not a new idea as far as being more efficient. A friend of mine at National Semiconductor and I had this discussion several years ago, and we even produced a few test transistors. The current problem you run into is that all CAD design tools and manufacturing processes are based on an XY grid, and it's difficult to design something that resembles a circle without increasing the physical transistor size which is counter productive to the overall design goal.

    This is a novel idea, but without lots of $$$ and large chip manufacturers willing to re-tool their entire FAB for this unique process, I don't see this being main stream any time soon.

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    Beau Schwabe

    IC Layout Engineer
    Parallax, Inc.

    Post Edited (Beau Schwabe (Parallax)) : 2/24/2010 7:51:55 AM GMT
    963 x 505 - 98K
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