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Vss and Vdd Pins — Parallax Forums

Vss and Vdd Pins

Alexander (Sandy) HapgoodAlexander (Sandy) Hapgood Posts: 360
edited 2010-02-28 23:12 in Propeller 1
There are two Vss and two Vdd pins on the DIP version of the propeller chip (P8X32A-D40). These are: 9 and 29 for Vss, 12 and 32 for Vdd.

The P8X32A-Q44 and P8X32A-M44 have four of each.

Do all Vdd pins and Vss pins need to be connected for the chip to be powered correctly or are they connected internally. Internally is the answer I'm wanting to hear! [noparse]:)[/noparse]


Regards,

Sandy Hapgood

Comments

  • LeonLeon Posts: 7,620
    edited 2010-02-22 18:34
    They MUST be connected, and each pair should be decoupled.

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    Amateur radio callsign: G1HSM
  • Bill HenningBill Henning Posts: 6,445
    edited 2010-02-22 18:35
    They all need to be connected.
    Alexander (Sandy) Hapgood said...
    There are two Vss and two Vdd pins on the DIP version of the propeller chip (P8X32A-D40). These are: 9 and 29 for Vss, 12 and 32 for Vdd.

    The P8X32A-Q44 and P8X32A-M44 have four of each.

    Do all Vdd pins and Vss pins need to be connected for the chip to be powered correctly or are they connected internally. Internally is the answer I'm wanting to hear! [noparse]:)[/noparse]


    Regards,

    Sandy Hapgood
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  • Alexander (Sandy) HapgoodAlexander (Sandy) Hapgood Posts: 360
    edited 2010-02-22 18:39
    Wow. That was fast. Bad news really does travel fast! Haha.

    Thanks,
    Sandy
  • davrandavran Posts: 12
    edited 2010-02-27 14:38
    i use only two of the supply pins, what might be the consequences? since the chip looks good

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  • RsadeikaRsadeika Posts: 3,837
    edited 2010-02-27 15:46
    Since I have been looking at the Propeller Manual today, I noticed on page 17, Hardware Connections, the diagram only shows the VSS, and VDD on the one side of the chip being used. Unless it is a typo in the book, I would go with the manuals illustration as being safe to implement.

    Ray
  • Toby SeckshundToby Seckshund Posts: 2,027
    edited 2010-02-27 15:50
    I always thought that not using the entire compliment of power pins would stress the internal silicon. This is the rumoured cause of the PLL failures.

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  • LeonLeon Posts: 7,620
    edited 2010-02-27 15:59
    Yes, the chip was designed to have all of the power and ground pins connected.

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    Leon Heller
    Amateur radio callsign: G1HSM
  • Miner_with_a_PICMiner_with_a_PIC Posts: 123
    edited 2010-02-27 16:01
    Davran >> On my desk I have a fried propeller chip (DIP version) caused (I suspect) by not connecting all the VSS and VDD pins. I ran the chip for quite some time at 5 MHz and occasionally at 80 MHz both with only one or two cogs running at a time. Then one day I launched all cogs @ 80 MHz and that ended badly with my prop non-functional within about 10 seconds. Upon investigation it was found that a low impedance between the VSS and VDD pins had manifested itself...something fried, shorting the chip internally. I suppose if you want to run very few cogs at a very low speed then you may get away with connecting only on VSS and VDD but that seems absurd, why risk reliability for the sake of a couple of minutes of soldering?? Take a look at this thread for more detail regarding the propeller's vulnerability to VSS to VSS and VDD to VDD deltas in voltage (note Chip's inputs)...

    http://forums.parallax.com/showthread.php?p=864936

    Ray >> I saw the connection scheme illustration in the user manual and after reading the above thread wondered why the Parallax team had not closed loop on the documentation to prevent misunderstandings.
  • Miner_with_a_PICMiner_with_a_PIC Posts: 123
    edited 2010-02-27 16:17
    One after thought... it is common practice to connect all VSS and VDD pins on an IC, perhaps this is the reason why all pins were not explicitly shown connected in the user manual. In my case I was being lazy with the prop that fried and I paid the price ($7.99). I now connect all VSS and VDD pins together, decouple well and over design the regulator (to reduce power supply ripple, a bit obsessive) on all designs/prototypes as reliability is very important for my applications.
  • HumanoidoHumanoido Posts: 5,770
    edited 2010-02-28 05:52
    Chip Gracey would have the definitive answer. I remember reading
    it's a good practice to connect all Vss together and all Vdd together
    to reduce noise effects. This becomes especially important with
    multiple prop chips. My early experiments have confirmed this.

    humanoido
  • Cluso99Cluso99 Posts: 18,069
    edited 2010-02-28 09:47
    All VDD and VSS pins MUST be connected and decoupled.

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  • Toby SeckshundToby Seckshund Posts: 2,027
    edited 2010-02-28 10:04
    On the SDRAMs, AVRs and CPLDs I have, the Vss and Vdd pins are scattered all over the place. They all have dire warnings about not connecting each and every one, even if some come under the title of "I/O", "DATA" or "ANALOG". I am sure that the Prop has all these warnings too. All of the pairs should be more than adiquately decoupled

    It might make the PCB layout a bit more "convenient" to pick and choose if they get used, but don't do it.

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  • LeonLeon Posts: 7,620
    edited 2010-02-28 10:46
    As an experiment once, with a 16-bit PIC with two pairs of Vdd and Vss pins, I left off one of the decoupling capacitors. I couldn't even program the chip until I added it.

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  • RsadeikaRsadeika Posts: 3,837
    edited 2010-02-28 12:28
    I just checked the next available source of information for this, PELabsFunBook-v1.1.pdf. On page 27, it shows that both sides of the chip are connected to a power source. The thing that I have not found yet is, any statements stating that if both sides are not connected, that the chip may not function properly. Since their have been a couple of posts using the terminology of "decoupling", I think that someone, maybe should define what decoupling means, in layman's terms, since there are some people that may not know what that is, like myself.

    I guess the next question to ask is, why does the chip have VDD, and VSS on both sides of the chip? Is it to balance out the pins on the dip version LOL?

    Ray
  • BradCBradC Posts: 2,601
    edited 2010-02-28 12:37
    Rsadeika said...


    I guess the next question to ask is, why does the chip have VDD, and VSS on both sides of the chip? Is it to balance out the pins on the dip version LOL?

    It's to help supply a low impedance path to both sides of the die. The smd chips have 4 sets of power pins. By not connecting a pin, you are asking the power paths across the die to carry far more current than they need to. This can have nasty side effects (like cooking the clock PLL).

    Always connect all power pins. Always decouple all power pins (connect a capacitor between them as close as is practical to the chip). Now I'll leave myself nicely open to ridicule by saying a good rule of thumb is a minimum of 0.1uF on each set of power pins. Low ESR caps are best. I just use monoblock ceramics as I buy them in packs of 1000.

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  • Toby SeckshundToby Seckshund Posts: 2,027
    edited 2010-02-28 13:01
    BradC

    There is nothing wrong in what you say. In the good old days the chips only had one set of power pins, byt then they didn't have so much in them and clocked slower. CMOS has much "sharper" switching edges and it is these edges that require good solid energy to be available. 0.1uF close in is a very good start, a larger "bulk" cap nearby is good.

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  • HumanoidoHumanoido Posts: 5,770
    edited 2010-02-28 14:04
    Using the diagram below, exactly what is the recommended physical
    position of decoupling capacitors?

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  • kwinnkwinn Posts: 8,697
    edited 2010-02-28 14:19
    I would recommend two 0.01uf capacitors, each as close to the Vdd/Vss pins on the side it is on as possible. One on 9 & 12, the other on 29 & 32.
  • Toby SeckshundToby Seckshund Posts: 2,027
    edited 2010-02-28 14:46
    Decoupling is one of those "Black Arts" that has no complete answer. You end up doing more and more for ever decreasing returns.

    No decoupling is just not an option.

    Minimal decoupling will get most things up and running when the conditions are near to perfect.

    Better decoupling will get all things rolling along even when life is a bit more hostile.

    Heavy decoupling will be needed when life is going to be really mean, as in overclocking.

    You can worry about all sorts of things, and build in bits to counteract them, but a 0.1uf ceramic on every Vdd and Vss, on every chip, together with a 10uF for the Prop and for every other 5 ordinary chips (evenly distributed) will be a solid start.

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    Post Edited (Toby Seckshund) : 2/28/2010 2:56:05 PM GMT
  • Beau SchwabeBeau Schwabe Posts: 6,566
    edited 2010-02-28 15:07
    It's really not a "black art ... that has no complete answer" ...

    http://forums.parallax.com/showthread.php?p=865046

    ... Inside the chip die itself, there is what's commonly called IR drop. It represents current drop due to resistance over a distance. The length wires inside the Chip have so many Ohms per square (typically .08 Ohms) and contribute to the internal 'R' value. By utilizing ALL of the Vss and Vdd pins you effectively are using the external wiring as a parallel resistor within the internal resistance of the wire within the die, thus reducing the IR effects over the entire chip.

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    IC Layout Engineer
    Parallax, Inc.
  • KyeKye Posts: 2,200
    edited 2010-02-28 16:52
    The reason Toby Seckshund says its a black art is because its near impossible to easily calculate what value of decoupling cap you should use.

    Thus your guessing about the value making the process a black art.

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  • Toby SeckshundToby Seckshund Posts: 2,027
    edited 2010-02-28 19:42
    I was always told that you should have "layered" decouplers that make up for the deficiencies in the others. That is, to have a 100pF + 1nF + 10nF ......... allowing for all the impedances in all of the frequencies.

    Without all those £20K+ cute toys to see what makes the differences, or not, it lurches towards educated guesswork.

    Fortunately, lobbing in a load of caps is so easy, although I suspect that having good quality energy available to an insuficient number of power pins, could make it worse for all those internals. So as everybody says, use all the power pins with some 100nF caps.

    Right, I'm off to find some apple juice, if those pesky elves haven't nicked it, again.

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    Post Edited (Toby Seckshund) : 2/28/2010 8:10:55 PM GMT
  • Beau SchwabeBeau Schwabe Posts: 6,566
    edited 2010-02-28 20:50
    Perhaps the attached visual will help.



    Toby Seckshund,

    "I was always told that you should have "layered" decouplers that make up for the deficiencies in the others. That is, to have a 100pF + 1nF + 10nF ......... allowing for all the impedances in all of the frequencies." - That is correct, but one reason this is true is due to the internal resistance within each capacitor which creates an·RC·filter at different frequency poles.· If the capacitors had no internal resistance, then it would just be an accumulative capacitor event.

    Yes, you can place several caps and you should be in good shape, but you should at least know why doing this helps.· It's not guess work if you understand the problem and know which direction to go with the solution.·





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    Beau Schwabe

    IC Layout Engineer
    Parallax, Inc.
    PROPIC.JPG
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  • SapiehaSapieha Posts: 2,964
    edited 2010-02-28 21:29
    Hi Beau Schwabe (Parallax)

    Nice picture.

    BUT I have one question?.

    Have COG's same placement on Die in conjunction to Power PIN's.

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    Nothing is impossible, there are only different degrees of difficulty.
    For every stupid question there is at least one intelligent answer.
    Don't guess - ask instead.
    If you don't ask you won't know.
    If your gonna construct something, make it·as simple as·possible yet as versatile as posible.


    Sapieha
  • Beau SchwabeBeau Schwabe Posts: 6,566
    edited 2010-02-28 22:17
    Sapieha,

    Here is an actual view of the current die...

    http://www.parallax.com/Portals/0/Images/Prod/0/PropDieDiagram.jpg

    ...you can see the power ring that goes around the outside perimeter of the die.· The picture that I posted earlier was just to get the idea across.· Please note in actuality, power and ground is picked off in multiple locations around the die.· In the current Propeller this means that some of this power passes through from one COG to the next as sort of a 'grid' archetecture.· The Propeller II will likely be closer to the example image I posted with a better power grid structure throughout the Chip.




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    Beau Schwabe

    IC Layout Engineer
    Parallax, Inc.

    Post Edited (Beau Schwabe (Parallax)) : 2/28/2010 10:22:22 PM GMT
  • SapiehaSapieha Posts: 2,964
    edited 2010-02-28 22:33
    Hi Beau Schwabe (Parallax)


    Thanks

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Nothing is impossible, there are only different degrees of difficulty.
    For every stupid question there is at least one intelligent answer.
    Don't guess - ask instead.
    If you don't ask you won't know.
    If your gonna construct something, make it·as simple as·possible yet as versatile as posible.


    Sapieha
  • Toby SeckshundToby Seckshund Posts: 2,027
    edited 2010-02-28 23:12
    Beau

    Thanks for the pics, Yes I do know something of the Minutiae of the problems, I was for many years in microwave transmission.

    I was just trying to stay at the hobbyist level.

    Good luck with the layouts, and if you mistakenly produce a few PLCC84 prop1 Bs, I'll have them.

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