Propeller I/O Pin Configuration?

jcwren

Is there a document that shows the structure of the I/O pin hardware topology? Often data sheets contain a pictorial diagram of the FET arrangement for an I/O pin, but so far I haven't seen that for the Propeller.

The reason I ask is I'm looking for what the pin looks like in an input configuration. I have a number of pins driving 2N7000 FETs. At boot-up, while the pins are still in an input configuration, the 2N7000's are going active. A pull-down is the correct solution, but I'd like to know what the largest value resistor I can safely use is.

--jc

Mike Green

There's no document that gives the I/O pin structure other than that it has a typical active pullup and pulldown FET that can both be turned off and an input FET with the gate connected to the I/O pin. There are substrate diodes reverse connected between the I/O pin and the Vdd/Gnd rails. All of these structures have a small amount of leakage shown on the datasheet on the order of 1uA to either supply rail. That's more than enough leakage to be able to turn on a 2N7000. Since the leakage amounts are maxima and the 2N7000's gate threshold range is quite wide, it's hard to say what the minimum pulldown value would be. I'd try something in the range of 220K to 470K.