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Propeller capability with asynchronous inputs — Parallax Forums

Propeller capability with asynchronous inputs

lzlz Posts: 3
edited 2010-01-07 02:31 in Propeller 1
I have a potential application that would require knowing an asynchronous state change on two separate inputs to within 5 uSec of their changes.
Is this possible with a propeller chip? Since interrupts are not available on the prop. chip and I can not poll for these events, how would this be done.
Thanks.........

Comments

  • Zap-oZap-o Posts: 452
    edited 2010-01-07 00:53
    I would thin it would be simple enough just use the ina register to monitor the inputs.
  • Zap-oZap-o Posts: 452
    edited 2010-01-07 01:56
    I forgot to mention that the propeller has 8 processors that run at 80Mhz. This little chip can do almost anything. The interrupts are not needed on the propeller because of the system counter, multi-core and blazing speed. You could simply run a loop in one cog (processor) that checks the status of the inputs and signals another cog of the "news" [noparse]:)[/noparse]
  • LawsonLawson Posts: 870
    edited 2010-01-07 02:02
    If you're willing to drop into assembly, 5usec is a good bit of time. At an 80Mhz clock that's almost 100 instructions for a polling loop that repeats every 5usec. (This would run in a seperate COG and update values in the HUB for the main program)

    A better way would be to use WAITPNE to wait for one of the pins to change state. Then grab CNT and use a bit of boolean logic to figure out which pin changed. With this method the input events could be detected with an accuracy of one clock cycle as long as they didn't happen too close together. (within limits, this should work well even in spin)

    Lawson

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  • Zap-oZap-o Posts: 452
    edited 2010-01-07 02:11
    Lawson you being up a great point but I must askt: are you saying that the WAITPNE could take 1 clock cycle in assembly? I was under the impression that no instruction was less than 4 clock cycles. Sorry if I got this wrong I am still digesting machine code - reason for my question.
  • LawsonLawson Posts: 870
    edited 2010-01-07 02:24
    WAITPNE takes 5 or more clock cycles to execute. The key is that it will exit it's wait state within one clock cycle of the pin state change it's looking for. There are then fixed delays until CNT and INA can be recorded for code to chew on. Since the extra delays are fixed they can be subtracted out and/or hidden with careful coding. The delay till saving INA could cause problems as this delay gives the pin a few clock cycles to change state again.

    Lawson

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Lunch cures all problems! have you had lunch?
  • Zap-oZap-o Posts: 452
    edited 2010-01-07 02:31
    Ahh, very elegant solution.
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