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Snes ppu

Pyr0mannPyr0mann Posts: 2
edited 2009-12-22 01:18 in Propeller 1
Has anyone looked at building the 2 PPU chips for the Super Nintendo in the prop?

I've seen the Hydra board with NES connectors, and the 512K RAM card.

I've seen the 6502 Propeller Laptop.

I was wondering if anyone has thought of linking the prop to a 65816 and external SRAM to build a ROM compatible SNES.

Comments

  • ericballericball Posts: 774
    edited 2009-12-20 21:22
    Not that I'm aware of. There are a couple of threads discussing emulating the NES with the Propeller, but nothing about the SNES. In general, emulation is a challenge. Additionally, interfacing to external hardware is a lesser, but still significant, challenge.

    One big challenge you may have is simply the number of pins. I just tried to find a pinout and wasn't able to. But I know the NES PPU had a completely separate bus to the cartridge.

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  • whickerwhicker Posts: 749
    edited 2009-12-21 07:38
    be warned,

    In console gaming systems, the video chips are way more advanced and complicated than the general purpose CPU feeding it. But by extension, they're way more specialized. The Propeller 1 could probably do a TMS9918, which has a similar scheme comprised of memory-mapped control registers and a port area with which to access the video RAM indirectly.

    The SNES's PPU's run ridiculously complicated state machines. They're tied to two Static RAM chips (not DRAM), and some screen modes hit every access. Any emulator I've seen doesn't even really try to duplicate their exact internal happenings. The clone systems use "stolen" chip masks as the producers didn't even bother with reverse engineering and producing a compatible circuit.

    You'd need an FPGA to even attempt to duplicate the behavior real-time. And the FPGA doesn't have the analog RGB output you'd need. And then you'd still need to throw in the NTSC encoder chip.

    In a different part of the system, a 65816 is just the core, there's some stuff surrounding it inside the 5A22 chip like the multiplier, a DMA controller, memory decoding circuitry with a somewhat non-intuitive secondary address bus for video DMA, and video count registers that can cause interrupts.
  • Pyr0mannPyr0mann Posts: 2
    edited 2009-12-22 01:18
    I figured on needing some kind of CPLD to interface to the 65816. And probably another one to deal with improving the interface between the RAM and the prop. Yes, I did notice the strange Buss A, Buss B interface.

    I knew it would be a stretch but I'd just hoped someone might be already trying.

    Thank you for the suggestion about the TMS9918.

    I was hoping to use it the way you would expect, as the hardware interface to a more traditional large memory processor system.
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