MAX127 Data Sheet How do I read the data from it Help me understand the data s
sam_sam_sam
Posts: 2,286
I am trying to write a Demo for this chip
I want to thank any one that can help me with this
Here is the data sheet
http://datasheets.maxim-ic.com/en/ds/MAX127-MAX128B.pdf
Digital Interface
The MAX127/MAX128 feature a 2-wire serial interface consisting of the SDA and SCL pins. SDA is the data I/O and SCL is the serial clock input, controlled by the master device. A2A0 are used to program the MAX127/MAX128 to different slave addresses. (The MAX127/MAX128 only work as slaves.) The two buslines (SDA and SCL) must be high when the bus is not in use.Table 1 shows the input control-byte format.I understand what they have in Table 1 I use this when I· wrote the demo for the MAX186
Typical Operating Circuit· shows only one pull-up resistor so which is it one or two
·External pull-up resistors (1kWor greater) are required on SDA and SCL to maintain I2C compatibility.
What do you do when you only have ONE Chip ?
Slave Address
The MAX127/MAX128 have a 7-bit-long slave address. The first four bits (MSBs) of the slave address have been factory programmed and are always 0101.The logic state of the address input pins (A2A0) determine the three LSBs of the device address (Figure 3). A maximum of eight MAX127/MAX128 devices can therefore be connected on the same bus at one time. A2A0 may be connected to VDD or DGND, or they may be actively driven by TTL or CMOS logic levels.The eighth bit of the address byte determines whether the master is writing to or reading from the MAX127/ MAX128 (R/W = 0 selects a write condition. R/W = 1selects a read condition).
Conversion Control
The master signals the beginning of a transmission with a START condition (S), which is a high-to-low transitionon SDA while SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition on SDA while SCL is high (Figure 4). The bus is then free for another transmission. Figure 5 shows the timing diagram for signals on the 2-wire interface. The address-byte, control-byte, and data-byte are transmitted between the START and STOP conditions. The SDA state is allowed to change only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit words. Nine clock cycles are required to transfer the data in or out of the MAX127/MAX128. (Figures 9 and 10).
Help me understand how I would writer a routine to be able to read this chip
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··Thanks for any·
·that you may have and all of your time finding them 
·
·
·
·
Sam
Post Edited (sam_sam_sam) : 12/13/2009 4:22:57 AM GMT
I want to thank any one that can help me with this
Here is the data sheet
http://datasheets.maxim-ic.com/en/ds/MAX127-MAX128B.pdf
Digital Interface
The MAX127/MAX128 feature a 2-wire serial interface consisting of the SDA and SCL pins. SDA is the data I/O and SCL is the serial clock input, controlled by the master device. A2A0 are used to program the MAX127/MAX128 to different slave addresses. (The MAX127/MAX128 only work as slaves.) The two buslines (SDA and SCL) must be high when the bus is not in use.Table 1 shows the input control-byte format.I understand what they have in Table 1 I use this when I· wrote the demo for the MAX186
Typical Operating Circuit· shows only one pull-up resistor so which is it one or two
·External pull-up resistors (1kWor greater) are required on SDA and SCL to maintain I2C compatibility.
What do you do when you only have ONE Chip ?
Slave Address
The MAX127/MAX128 have a 7-bit-long slave address. The first four bits (MSBs) of the slave address have been factory programmed and are always 0101.The logic state of the address input pins (A2A0) determine the three LSBs of the device address (Figure 3). A maximum of eight MAX127/MAX128 devices can therefore be connected on the same bus at one time. A2A0 may be connected to VDD or DGND, or they may be actively driven by TTL or CMOS logic levels.The eighth bit of the address byte determines whether the master is writing to or reading from the MAX127/ MAX128 (R/W = 0 selects a write condition. R/W = 1selects a read condition).
Conversion Control
The master signals the beginning of a transmission with a START condition (S), which is a high-to-low transitionon SDA while SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition on SDA while SCL is high (Figure 4). The bus is then free for another transmission. Figure 5 shows the timing diagram for signals on the 2-wire interface. The address-byte, control-byte, and data-byte are transmitted between the START and STOP conditions. The SDA state is allowed to change only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit words. Nine clock cycles are required to transfer the data in or out of the MAX127/MAX128. (Figures 9 and 10).
Help me understand how I would writer a routine to be able to read this chip
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
··Thanks for any·
·that you may have and all of your time finding them ·
·
·
·
Sam
Post Edited (sam_sam_sam) : 12/13/2009 4:22:57 AM GMT
Comments
What MCU are you using?
Leon
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Amateur radio callsign: G1HSM
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··Thanks for any·
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Sam
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- Stephen