How many address lines can you drive at once? I don't deal with video modes enough to grok the setup. VGA mode can do 8 right? Do you have a full example I could test?
Ah, gotcha. Correct, the video mode can drive a maximum of 8 lines. This lets you read in 256 bytes, as 64 longs, in a single loop. I am setting this up to read a 256 byte block to cog RAM, then dump that to Hub RAM. Then you would adjust the the address lines (except the low 8 of course), then run the thing again. In this mode you would never actually specify the low 8 bits of the address. You would either read or write everything in 256-byte aligned block bursts. I was planning to do a Read-Ahead and Write-Behind structure, nearly identical to the structure I used in the FSRW block layer, though I don't have a chip to test it with yet.
Jonathan
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lonesock
Piranha are people too.
I am looking forward to seeing it, and the potential speed boost to fsrw [noparse]:)[/noparse]
Nice work!
lonesock said...
Ah, gotcha. Correct, the video mode can drive a maximum of 8 lines. This lets you read in 256 bytes, as 64 longs, in a single loop. I am setting this up to read a 256 byte block to cog RAM, then dump that to Hub RAM. Then you would adjust the the address lines (except the low 8 of course), then run the thing again. In this mode you would never actually specify the low 8 bits of the address. You would either read or write everything in 256-byte aligned block bursts. I was planning to do a Read-Ahead and Write-Behind structure, nearly identical to the structure I used in the FSRW block layer, though I don't have a chip to test it with yet.
Jonathan
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ www.mikronauts.com Please use mikronauts _at_ gmail _dot_ com to contact me off-forum, my PM is almost totally full Morpheusdual Prop SBC w/ 512KB kit $119.95, Mem+2MB memory IO board kit $89.95, both kits $189.95 Propteus and Proteus for Propeller prototyping 6.250MHz custom Crystals run Propellers at 100MHz Las - Large model assembler for the Propeller Largos - a feature full nano operating system for the Propeller
Maybe we can talk Bill or mctrivia into sending you a PSRAM module. The device being used has 20ns Asynchronous SRAM mode by default and is really cheap $10/16MB per device. A virtual memory subsystem would be possible with that [noparse]:)[/noparse]
Cluso99 said...
I MUST state again, that the output address from 1 cycle cannot necessarily be followed by a read in the next cycle, no matter how you do it (i.e. by multiple cogs). ....
Now that we have theoretical confirmation from Chip (with your and Kuroneko's help of course), your post needs to be revised. Thank goodness, no more FUD.
Thank goodness the margin is near 28ns at 80MHz system clock. This allows cheap solutions like PSRAM with 20ns access in asynchronus SRAM mode. PSRAM would work in back to back set address/read data or 5COG collection since the later method has 25ns separation between sample points.
Now onward and upward ....
@lonesock,
I've implemented a write routine similar to your read. The problem I face is regardless of what I do, I can't change the inter-access waitvid time. I'll start another thread.
Yep, I've wished for a way to re-sync the internal "pixels left" counter on the video hardware. The best I can do is change the vscl register to a faster repeat (fewer "pixels") for the times I'm not using the video hardware, and disable any clock pin. As you can see in my code above, I'm also trying to re-use the last few data values in the "colors" register, and make the vscl pixel period larger, so my turnaround catches the waitvid with a minimum of wasted time.
Jonathan
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lonesock
Piranha are people too.
@lonesock,
I'll have to post code later. I've no more time for it this week after spending half a day on an optimized write ... half as fast as the read ... grimace. The I tried the re-sync, but the scope says it's not working. Gotta tend to other business the rest of the week. I'll get back to it when I have room to breathe[noparse]:)[/noparse] Later.
Yes it was fun to try and speculate the timing and then prove it. I will update the timing diagram based on Chip's explainationed the states. A picture is worth a thousand words, as they say.
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I MUST state again, that the output address from 1 cycle cannot necessarily be followed by a read in the next cycle, no matter how you do it (i.e. by multiple cogs).
Maybe so, so lets use two counters to generate the low two bits of the address, we can now do bursts of 4 reads or writes at the clock rate.
Or just use the video shifter as lonesock suggested. Sorry I had skipped ahead to make the first part of this reply.
Maybe so, so lets use two counters to generate the low two bits of the address, we can now do bursts of 4 reads or writes at the clock rate.
You are absolutely correct of course. This entire thread exists primarily because the OP (conveniently for his own purposes) ignored the idea that one can use 5 COGs to read 4 bytes at a time back to back as long as the memory is fast enough.
Now that we have good caching implementations, the topic is mostly irrelevant unless you want to build a big video buffer
Jazzed:
Yes, and thanks to a challenge, given me by you, I have an interest in a big video buffer. Besides I am doing this with 10ns SRAM for my Amiga Clone, which now has a name; NuAmi.
Comments
Jonathan
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lonesock
Piranha are people too.
Nice work!
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www.mikronauts.com Please use mikronauts _at_ gmail _dot_ com to contact me off-forum, my PM is almost totally full
Morpheusdual Prop SBC w/ 512KB kit $119.95, Mem+2MB memory IO board kit $89.95, both kits $189.95
Propteus and Proteus for Propeller prototyping 6.250MHz custom Crystals run Propellers at 100MHz
Las - Large model assembler for the Propeller Largos - a feature full nano operating system for the Propeller
Thank goodness the margin is near 28ns at 80MHz system clock. This allows cheap solutions like PSRAM with 20ns access in asynchronus SRAM mode. PSRAM would work in back to back set address/read data or 5COG collection since the later method has 25ns separation between sample points.
Now onward and upward ....
@lonesock,
I've implemented a write routine similar to your read. The problem I face is regardless of what I do, I can't change the inter-access waitvid time. I'll start another thread.
Yep, I've wished for a way to re-sync the internal "pixels left" counter on the video hardware. The best I can do is change the vscl register to a faster repeat (fewer "pixels") for the times I'm not using the video hardware, and disable any clock pin. As you can see in my code above, I'm also trying to re-use the last few data values in the "colors" register, and make the vscl pixel period larger, so my turnaround catches the waitvid with a minimum of wasted time.
Jonathan
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
lonesock
Piranha are people too.
I'll have to post code later. I've no more time for it this week after spending half a day on an optimized write ... half as fast as the read ... grimace. The I tried the re-sync, but the scope says it's not working. Gotta tend to other business the rest of the week. I'll get back to it when I have room to breathe[noparse]:)[/noparse] Later.
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Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
Or just use the video shifter as lonesock suggested. Sorry I had skipped ahead to make the first part of this reply.
Now that we have good caching implementations, the topic is mostly irrelevant unless you want to build a big video buffer
Yes, and thanks to a challenge, given me by you, I have an interest in a big video buffer. Besides I am doing this with 10ns SRAM for my Amiga Clone, which now has a name; NuAmi.