With that memory arbiter ... It is still posible to have it in one cycle.
In that maner ... If arbiter see att it is same addres it simple output write data to Reader in same time write same data to memory position
Regards
Christoffer
Ps. if I'm are correct .... that has NAME ...... Pass trough
My concern are mostly ... How much silikone it will take
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Nothing is impossible, there are only different degrees of difficulty. For every stupid question there is at least one intelligent answer. Don't guess - ask instead. If you don't ask you won't know. If your gonna construct something, make it·as simple as·possible yet as versatile as posible.
Yes YOU are correct
LOCKs ......
Sorry my bad English.
And yes I refering to "I thought you were referring to any hub memory access and trying to overlap 2 cogs access simultaneously."
"Pass trough" was direct trabslation fro Swedish". Thanks
And with that system it can be bigger Troughput in memory.
Regards
Christoffer
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Nothing is impossible, there are only different degrees of difficulty. For every stupid question there is at least one intelligent answer. Don't guess - ask instead. If you don't ask you won't know. If your gonna construct something, make it·as simple as·possible yet as versatile as posible.
Sapieha said "And yes I refering to "I thought you were referring to any hub memory access and trying to overlap 2 cogs access simultaneously.""
For overlapped 2 cog access,·the memory has to run twice as fast, with an access on both clock edges. I think this is not going to be possible, but Chip can answer this.
Chip:·· Cog Priority Hub Access
You·mentioned at one stage perhaps giving cogs priority access. From what I understand, there will be a block read/write instruction which also transfers 4 longs per access, and an access every 1 in 8 clocks.
Could this block read/write instruction be given priority such that any unused slots by other cogs could be utilised by·this cog?
If more than 1 cog were issuing a block read/write then it would be acceptable to either give priority to the first cog executing this instruction (easiest)·or share the priority.
I realise this would lose determinism for this cog only, but that would be an acceptable loss for this particular instruction. If determinism were required it could be calculated manually using CNT.
Otherwise, would it be possible for each cog to have a bit in a register to set priority, such that any read/write hub instruction (or block instruction only) could utilise unused slots?
The same mechanism could be used for coginit loading of cog ram which would speed this up. It would be nice to be able to limit the load length on coginit too.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Links to other interesting threads:
I have been thinking about what Chip and Bill have suggested. I was wondering if the following access would be feasible...
For instructions where the source and/or destination is indirect (i.e. not immediate), since we only use the lower 9 bits, could the upper bits be used to set access to the fifo ?· e.g. $000-$1FF is access to cog ram, $200-$27F is direct access to the fifo (as 128 longs)
This could permit the standard instructions MOV/AND/OR/ROL/SHR/SUB/CMP/etc to have random access to the fifo as additional cog memory for variables.
I understand that the normal cog ram·will have·4-way simultaneous access whereas the fifo presumably does not. So instructions accessing the fifo may require 2 clocks if two successive fifo instructions were executed. Instructions where the source and destination were both in the fifo would fail.
An extension to this could be... $10000-$100FF is direct access to the fifo (as 256 words) and $20000-$201FF is direct access to the fifo (as 512 bytes). This method would allow for possible future expansion of the fifo to·64KB (16K longs) e.g. Prop III?
If word and byte access·were provided as suggested above, the upper bits would be zeroed when read from the fifo, and ignored when written to the fifo.
Based on the above, could it be possible for one cog to have a larger fifo?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Links to other interesting threads:
Now comming my next ...(BAD) idea. Much radical.
First one Question?.
Have You place for 2 EXTRA instructions?. And posiblity to modify RET instruction.
1. JUMP-LMM = LMM direct jump in HUB ....... If posible - entire addres space in HUB .
2. CALL-LMM = LMM direct call in HUB ......... If posible - entire addres space in HUB .. With modified RET that hold in COG last CALL addres.
That can Give Propeller II ---- 2 types of EXECUTION type of programs with not need for kernel stub to LMM in COG ( next entire COG can be used as REGISTERS else BUFFERS).
One tecnical Question about ..... Propeller II pakage.
On propeller I - QFTP .... XTals pins are side by side.
Is It posible to Place in Propeller II one GND-ground pad betwen them .... For posibility to build GND-barier on PCB´s both sides.
That with that fine delay betwen pins on that pakage give no posibility to place TRACE barier betwen that 2 pins.
That barier give more reliable Frequency from XTal.
IF? ---- Chip inbuild any like RTC I mentioned ......... that GND barier need be on both XTal´s for precision frequeny.
Regards
Christoffer Jönsson
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Nothing is impossible, there are only different degrees of difficulty. For every stupid question there is at least one intelligent answer. Don't guess - ask instead. If you don't ask you won't know. If your gonna construct something, make it·as simple as·possible yet as versatile as posible.
Comments
With that memory arbiter ... It is still posible to have it in one cycle.
In that maner ... If arbiter see att it is same addres it simple output write data to Reader in same time write same data to memory position
Regards
Christoffer
Ps. if I'm are correct .... that has NAME ...... Pass trough
My concern are mostly ... How much silikone it will take
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
For every stupid question there is at least one intelligent answer.
Don't guess - ask instead.
If you don't ask you won't know.
If your gonna construct something, make it·as simple as·possible yet as versatile as posible.
Sapieha
Post Edited (Sapieha) : 12/4/2009 6:29:33 AM GMT
I think it is called write-through.
However, I misunderstood what you were after. You are referring to the LOCKs. (look means see)
I thought you were referring to any hub memory access and trying to overlap 2 cogs access simultaneously.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
Yes YOU are correct
LOCKs ......
Sorry my bad English.
And yes I refering to "I thought you were referring to any hub memory access and trying to overlap 2 cogs access simultaneously."
"Pass trough" was direct trabslation fro Swedish". Thanks
And with that system it can be bigger Troughput in memory.
Regards
Christoffer
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
For every stupid question there is at least one intelligent answer.
Don't guess - ask instead.
If you don't ask you won't know.
If your gonna construct something, make it·as simple as·possible yet as versatile as posible.
Sapieha
For overlapped 2 cog access,·the memory has to run twice as fast, with an access on both clock edges. I think this is not going to be possible, but Chip can answer this.
Chip:·· Cog Priority Hub Access
You·mentioned at one stage perhaps giving cogs priority access. From what I understand, there will be a block read/write instruction which also transfers 4 longs per access, and an access every 1 in 8 clocks.
Could this block read/write instruction be given priority such that any unused slots by other cogs could be utilised by·this cog?
If more than 1 cog were issuing a block read/write then it would be acceptable to either give priority to the first cog executing this instruction (easiest)·or share the priority.
I realise this would lose determinism for this cog only, but that would be an acceptable loss for this particular instruction. If determinism were required it could be calculated manually using CNT.
Otherwise, would it be possible for each cog to have a bit in a register to set priority, such that any read/write hub instruction (or block instruction only) could utilise unused slots?
The same mechanism could be used for coginit loading of cog ram which would speed this up. It would be nice to be able to limit the load length on coginit too.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
I have been thinking about what Chip and Bill have suggested. I was wondering if the following access would be feasible...
For instructions where the source and/or destination is indirect (i.e. not immediate), since we only use the lower 9 bits, could the upper bits be used to set access to the fifo ?· e.g. $000-$1FF is access to cog ram, $200-$27F is direct access to the fifo (as 128 longs)
This could permit the standard instructions MOV/AND/OR/ROL/SHR/SUB/CMP/etc to have random access to the fifo as additional cog memory for variables.
I understand that the normal cog ram·will have·4-way simultaneous access whereas the fifo presumably does not. So instructions accessing the fifo may require 2 clocks if two successive fifo instructions were executed. Instructions where the source and destination were both in the fifo would fail.
An extension to this could be... $10000-$100FF is direct access to the fifo (as 256 words) and $20000-$201FF is direct access to the fifo (as 512 bytes). This method would allow for possible future expansion of the fifo to·64KB (16K longs) e.g. Prop III?
If word and byte access·were provided as suggested above, the upper bits would be zeroed when read from the fifo, and ignored when written to the fifo.
Based on the above, could it be possible for one cog to have a larger fifo?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: CPUs Z80 etc; Micros Altair etc;· Terminals·VT100 etc; (Index) ZiCog (Z80) , MoCog (6809)
· Search the Propeller forums·(uses advanced Google search)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
Now comming my next ...(BAD) idea. Much radical.
First one Question?.
Have You place for 2 EXTRA instructions?. And posiblity to modify RET instruction.
1. JUMP-LMM = LMM direct jump in HUB ....... If posible - entire addres space in HUB .
2. CALL-LMM = LMM direct call in HUB ......... If posible - entire addres space in HUB .. With modified RET that hold in COG last CALL addres.
That can Give Propeller II ---- 2 types of EXECUTION type of programs with not need for kernel stub to LMM in COG ( next entire COG can be used as REGISTERS else BUFFERS).
REGARDS
Christoffer J
One tecnical Question about ..... Propeller II pakage.
On propeller I - QFTP .... XTals pins are side by side.
Is It posible to Place in Propeller II one GND-ground pad betwen them .... For posibility to build GND-barier on PCB´s both sides.
That with that fine delay betwen pins on that pakage give no posibility to place TRACE barier betwen that 2 pins.
That barier give more reliable Frequency from XTal.
IF? ---- Chip inbuild any like RTC I mentioned ......... that GND barier need be on both XTal´s for precision frequeny.
Regards
Christoffer Jönsson
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
For every stupid question there is at least one intelligent answer.
Don't guess - ask instead.
If you don't ask you won't know.
If your gonna construct something, make it·as simple as·possible yet as versatile as posible.
Sapieha