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Regarding propeller

sanketsanket Posts: 28
edited 2009-11-04 10:51 in Propeller 1
Hi all,
I asked you guys about the carry flag and zero flag set during the instruction execution.
I am sorry, but i still have some doubt about it or probably, i misunderstood.
I was informed that, for ROR operation, the carry bit should be set before the instruction executes. So, the question is does this phenomenon remains same for the other instructions?
Because, I went through propeller manual (page - 380) ,MINS operation. And its written that "carry flag is set if signed Svalue1 is less than signed Svalue2"
So, In this case, the carry flag should be set after the execution of the instruction. So, i am confused.
I will be really thankful to you, if i will be directed right.
Thank You

Regards
Sanket Shah

Comments

  • AleAle Posts: 2,363
    edited 2009-10-30 11:03
    Dear Sanket,

    There are instructions that take the carry (or zero) flag as an argument and there are others that do not.
    ROR does not use C as an argument, only as a result.
    RCR, on the other hand, does use C as an argument because it is rotated from left (it is input in the MSB) to the right. So, yes C has to be set to the correct value before you execute RCR (or any other instruction that needs the flag as argument.

    Remember that to get the modified flag (result) you have to use wc or wz depending on the flag (or both) you need/want.

    I hope it is clear, if not please ask again.

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  • sanketsanket Posts: 28
    edited 2009-10-30 12:21
    Hello Ale,
    Thank You very much for your instant response.
    So, did you mean that, in ROR, there is no need to write the carry flag before the instruction is executed? carry flag of the result is only written if 24th bit in the instruction is 1?
    Is that u mean to say?
    For example- ROR D,S = 001000 0010 1111 000000001 000000010
    First, i will fetch the destination and source value (both are 32 bits).
    suppose, S value says to rotate the D value by 5'b00010
    Now, i am rotating the D value by 2.
    So, as per the instruction, carry flag is not set, so i dont have to set the 24th bit of the result i got in D.
    and, if carry flag in the instruction (24th bit) in set, then i will have to set the 24th bit of the result (which is carry bit).
    Can you please, let know about my understanding for the upper ROR instruction.
    And in RCR operation what happens to the same instruction given above (assume with RCR's opcode).

    Thank You once again for your reply.

    Regards
    Sanket Shah
  • MagIO2MagIO2 Posts: 2,243
    edited 2009-10-30 12:28
    That's one of the nice features that make the propeller so unique. In all other microcontrollers/-processors that I worked with before, your flags will always be set according to the result and instructions that write to a destination do so in any case. In the propeller you can decide in which flags you are interested and if you really want to write back the result. For each and every PASM instruction you can define that and each and every instruction can be conditionally executed depending on the combination of flags.

    If you have a look at the compiled cmp and sub instructions you will find that the only difference in those commands is the NR/WR setting - which is a compiler default.

    cmp x, y
    is the same as
    sub x, y NR

    sub x, y
    it the same as
    cmp x,y WR

    The opcode of the instruction (the 6 MSBs) is exactly the same.

    And if you have a look into the SPIN interpreter sourcecode you can see how this·feature·allows to have an interpreter in only 512 instructions.

    Did someone port the SPIN interpreter to another microcontroller yet? Would be interesting to see how much bigger the code would then be.

    Post Edited (MagIO2) : 10/30/2009 12:34:14 PM GMT
  • AleAle Posts: 2,363
    edited 2009-10-30 13:46
    sanket:

    If the value contained in the flag is important for some next instruction then you have to specify the wc or wz effect.

    Again: yes you do not need to modify the C flag before ROR unless it is used by some other instruction like in this example:

       cmp  x, y   wc, wz     ' this will modify Z & C
   ror  zz, #5                ' ROR does not use C but you need the value in the next instruction
   muxc   zz, #1      ' this instruction needs C but the ROR had to be done before

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  • sanketsanket Posts: 28
    edited 2009-10-30 14:01
    Hello Ale,
    But what if i dont know about the next instruction.

    Regards
    Sanket Shah
  • AleAle Posts: 2,363
    edited 2009-10-30 14:25
    sanket said...
    But what if i dont know about the next instruction.

    Well, if you do not know... read the manual and find out if it is needed for what you want or not...! They are normally used in comparisons, shifts/rotates, addition/subtraction, conditional jumps...

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    OMU for the pPropQL/020 propeller.wikispaces.com/OMU
  • sanketsanket Posts: 28
    edited 2009-11-02 20:23
    Dear Ale,
    Here is some confusion.
    I thought that, i am suppose to modify the C flag and Z flag in 32 bit in the instruction itself (25th and 24th bit), because there is C and Z field in 32 bit instruction also.
    But, as per your answer, C and Z flag are the global flags for one processor, and 25th and 24th bit of the instruction indicates to change the global C and Z flags depends on the operation.
    So, the instruction which takes C flag as an argument that is the global C flag, not the C field in the instruction.
    Can u please let me know if i am in right direction??
    Thank You very much for your guidance.

    Regards
    Sanket Shah

    Post Edited (sanket) : 11/2/2009 8:43:03 PM GMT
  • jazzedjazzed Posts: 11,803
    edited 2009-11-02 22:26
    sanket said...
    Dear Ale,
    Here is some confusion.
    I thought that, i am suppose to modify the C flag and Z flag in 32 bit in the instruction itself (25th and 24th bit), because there is C and Z field in 32 bit instruction also.
    But, as per your answer, C and Z flag are the global flags for one processor, and 25th and 24th bit of the instruction indicates to change the global C and Z flags depends on the operation.
    So, the instruction which takes C flag as an argument that is the global C flag, not the C field in the instruction.
    Can u please let me know if i am in right direction??
    Thank You very much for your guidance.

    Regards
    Sanket Shah

    As Ale has explained this already, I thought you might benefit from a different but equivalent answer.

    Bit 24/25 of an instruction are commands to the instruction from the user to set or not set the state of the carry/zero flag to the global bit.

    If the instruction bits are not set, the global bits will not be changed. Else if the instruction bits are set as indicated by WC,WZ in the source, the global bits will be set to whatever/however the instruction evaluates.

    I hope this helps clear your doubts.
  • sanketsanket Posts: 28
    edited 2009-11-03 00:51
    Dear jazzed,
    Thank you very much for your reply.
    This will help me a lot.
    Now, I think i am pretty much cleared with the doubt i had.
    Thanx a lot once again.
    It would have been difficult without your support to move forward.

    Regards
    Sanket Shah
  • StefanL38StefanL38 Posts: 2,292
    edited 2009-11-03 06:15
    Hello Sanket,

    as far as I understand it the C-flag and the Z-flag are only modified if an instruction has a certain result. Different instructions set or clear one or both flags
    on different results. You can change the predefined behavour of the commands by specifying effects. See Effects ( WC, WZ, WR, NR ) in the propeller-manual
    on page 291.

    So one kind to set or clear a flag is to execute a operation which you select to just get the flag set or cleared.
    To your question I think so.

    But I would like to ask a complete different question. In your project is it excplicit forbidden to use a REAL Propeller to find out how it works ?
    Do have to do EVERYTHNG theoretically ? What do you think about using a simulator like GEAR ?

    best regards

    Stefan
  • sanketsanket Posts: 28
    edited 2009-11-03 07:29
    Hello stefan,
    Thank you for your reply.
    Yes, it is necessary to know the exact operation of the propeller.
    Because i am making multi-core architecture based on the propeller operation and also based on its instructions sets only.
    i am working on such architecture which can execute all the instruction provided in datasheet of the propeller.
    So, I am making the hardware which can execute the assembly or spin program. So whatever the code we write in assembly or spin language, the hardware will perform the same operation specified.
    I hope you have got my point now.
    If no, then please ask me. I will be thankful to inform you guys about my project.

    Best regards
    Sanket Shah
  • heaterheater Posts: 3,370
    edited 2009-11-03 07:59
    So is this going to be an FPGA? Created with Verilog or VHDL?

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  • StefanL38StefanL38 Posts: 2,292
    edited 2009-11-03 09:38
    Yes I have to ASK again

    is it forbidden for you to BUY a Propeller-Chip + EEPROM + 5MHz-Chrystal + MAX232 + some Capacitors to have a SECOND possability to ANALYSE how the propeller works ?
    (this would be an amount of around 20 dollars without shipping)

    is it forbidden for you to USE a simulator like GEAR to have a THIRD possability how the propeller works ?

    best regards

    Stefan
  • MagIO2MagIO2 Posts: 2,243
    edited 2009-11-03 10:25
    Don't you see any legal issues in re-engeneering the propeller?
  • heaterheater Posts: 3,370
    edited 2009-11-03 10:36
    The main issue I see in creating I Prop clone is that it requires a Spin interpreter, the boot loader code and the various tables and fonts in ROM. all of these are subject to copyright. Looks like it would be very hard to create a "clean room" re-implementation of the existing interpreter that operates exactly as the original and fits in 496 longs. Copying the fonts and tables is right out.

    For personal use perhaps no one worries.

    So Sanket, what is your goal with this project?

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  • jazzedjazzed Posts: 11,803
    edited 2009-11-03 19:52
    heater said...
    The main issue I see in creating I Prop clone is that it requires a Spin interpreter, the boot loader code and the various tables and fonts in ROM. all of these are subject to copyright. Looks like it would be very hard to create a "clean room" re-implementation of the existing interpreter that operates exactly as the original and fits in 496 longs. Copying the fonts and tables is right out.?
    If you want to make a clone, I agree. However, I'm not sure one needs to produce all of that to have a viable solution (other alternatives already exist thanks to you heater, ImageCraft, RossH, and many others). I'm seriously considering an alternative that implements the PASM instruction set and N*COGS but puts HUB RAM (and ROM space) on an external bus for memory flexibility. A question would be to Parallax on the possibility of licensing their patented IP. Capable FPGAs are cheap enough to make sense, and I already have COG and HUB features written and simulated in Verilog. I'm quite sick of waiting for Propeller II.

    Post Edited (jazzed) : 11/3/2009 8:14:10 PM GMT
  • heaterheater Posts: 3,370
    edited 2009-11-03 23:51
    Does Parallax have any patents ?

    I must say COGS in FPGA and external RAM is an interesting idea.
    Is it really possible to get 8 GOGs and HUB logic and timers/video into a single FPGA?
    Is it possible to get the RAM speed externally ?

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  • Mike GreenMike Green Posts: 23,101
    edited 2009-11-04 00:01
    This has been discussed on this forum before. What I gather is that the general solution to IP protection for Parallax is to use service, innovation and trade secrets where appropriate (hence the lack of disclosure for the Basic Stamp bytecodes) for protection from duplication and openness and innovation for protection from claims by others to the same IP.
  • jazzedjazzed Posts: 11,803
    edited 2009-11-04 02:02
    heater said...
    Does Parallax have any patents ?

    I must say COGS in FPGA and external RAM is an interesting idea.
    Is it really possible to get 8 GOGs and HUB logic and timers/video into a single FPGA?
    Is it possible to get the RAM speed externally ?

    Was going to say "patented IP (if any)."

    Not being an FPGA expert, so I can't say exactly what is possible, but there are some very
    attractive sub $200.00 solutions Spartan 3E here and Spartan 3 here.
    Those boards have features we all love: keyboard, VGA, serial port.
    They also have external memory, user Flash, and device Flash.

    The Spartan 3E 1200K has up to 500Kbits block/global memory and ~1200K CLBs. My experience
    in the corporate world with FPGAs tells me "start big and cost reduce." Going the other way can yield
    optimization nightmares. Once a gross design is tested, one can look at smaller variations.

    More analysis is necessary and there are forum members who have been down the road a little already.

    Sanket, I can move this discussion to a new thread if you like.
  • sanketsanket Posts: 28
    edited 2009-11-04 07:31
    Hello all,
    It seems like hot environment created because of me.
    first of all, I would like to thank you all guys who helped me out and who spent time for replying me.
    let me tell you the whole story.
    I am the student of electrical engineering and its my final project going on with propeller architecture.
    The purpose for choosing propeller is just to learn the basic programming skills (in verilog HDL) to design hardware.
    In my final project, i wanted to design processor and i made search in google regarding the architecture of the processor.
    Finally, I changed my mind to design the multi-core architecture (which, the propeller is).
    So, this is just a school project, nothing much.
    I think, to design the whole propeller chip clone, i need spin interpreter, boot loader and propeller kit as well.
    Even, I am not using any software given by you. So, its not possible for me to design the whole architecture alone including boot loader, spin interpreter etc.
    Even, I am not dealing with video part in the project.
    I am not doing any research or something else or I don't even want to copy your design for the future use.
    This is just a part of learning programming skill by using your design.
    I hope, now you guys get my point clearly.
    If no then , feel free to ask me. Because, i have an unpaid debt for you guys.
    Cause i would not have came to know about many fundamentals of the processor design without your technical support.

    Best regards
    Sanket Shah
  • Nick MuellerNick Mueller Posts: 815
    edited 2009-11-04 08:07
    > Is it really possible to get 8 GOGs and HUB logic and timers/video into a single FPGA?

    If I remember correctly, Parallax is making the design on FPGAs. Somewhere I read, that the Prop II exists on an FPGA.
    Maybe not the full speed, certainly much more expensive than the final chip. But perfect for verifying the logic.

    I'm a FPGA-idiot!


    Nick

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  • AleAle Posts: 2,363
    edited 2009-11-04 09:36
    At least the propeller II is (was) developed in a Stratix II device. (Maybe more than one?) Those devices cost > 1000€ apiece. I'd really would like to know how the prop I was developed if it was also a FPGA to ASIC or how.

    Nick: I'm merging a FPGA and a prop in a board, maybe it would be a good start for you (too) if you are interested smile.gif. The FPGA can be bought from Reichelt.

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  • Cluso99Cluso99 Posts: 18,069
    edited 2009-11-04 09:56
    sanket:

    You probably need to look at the instruction manual (pasm section) and the pasm reference sheet. Once you understand the philosophy behind the flag usage and the wc, wz and wr bits plus the 4 conditional execution bits, and the IdSDeR pipeline, the method Chip used in the design will become obvious and the FPGA code will become much easier for this section of the emulation. The actual c & z generation logic is quite simple.

    The harder part I found was trying to simplify the barrel shifter, but again as you reduce what is happening you will find it fits a very neat/efficient set of logic.

    I was using a Spartan 3A (Avnet kit) and verilog, but shelved the project for a while.

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    · Home of the MultiBladeProps: TriBlade,·RamBlade,·SixBlade, website
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    · Prop Tools under Development or Completed (Index)
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    · Search the Propeller forums·(uses advanced Google search)
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  • Nick MuellerNick Mueller Posts: 815
    edited 2009-11-04 10:51
    > Nick: I'm merging a FPGA and a prop in a board, maybe it would be a good start for you (too) if you are interested smile.gif

    I fear that! wink.gif
    There are so many things that could be done easier with an CPLD or FPGA. Especially for glue-logic. I think the Prop is a perfect match for that. High speed time critical stuff.

    Oh well! So many girls ... er ... ideas, so little time!

    Hey! How about Prallax about building such a board? They do have expertise in FPGAs (reading their history).


    Nick

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