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regarding propeller

sanketsanket Posts: 28
edited 2009-10-30 10:40 in Propeller 1
Hi all,
I am a student and my project is on propeller.
I have a little query regarding the carry and zero flag written.
On page no-400 of propeller manual, there is an instruction ROL.
So, the question is from which register the carry flag set to the 31st bit.
Is this carry bit set to the 31st bit of the value stored in the destination value before performing operation OR it is set to the 31st bit of the result we get after operation?

Thank You

Sanket Shah

Comments

  • James LongJames Long Posts: 1,181
    edited 2009-10-24 20:09
    My understanding, is that the flag is for the result of the operation.

    So for the carry flag is not important on the value, just the result of the command.

    James L

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  • Mike GreenMike Green Posts: 23,101
    edited 2009-10-24 20:13
    On the ROL instruction, the carry flag is set to the 31st bit before the shift is performed. If you're doing a single bit shift, this is the bit that is shifted from bit 31 to bit 0 when the actual shift is performed. It's not particularly useful if you're doing a multi-bit rotate.
  • ericballericball Posts: 774
    edited 2009-10-24 20:14
    If the WC effect is specified, the C flag is set equal to the destination register's original bit 31. Note: this is true even if the source register / immediate value is not 1.

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  • StefanL38StefanL38 Posts: 2,292
    edited 2009-10-24 22:09
    Hello Sanket,

    do you already have a propeller-chip ?

    If yes you can use http://www.insonix.ch/propeller/objects/PASD_05.zip
    to analyse things like this in real.

    Next way to do it is to write a PASM-program that stores the result of the operation in a variable accessable in SPIN
    and then do a binary output to PST.EXE to see what has happend or use different conditional jumps like if_c, if_z
    to return different results
    or switch on different LEDs

    best regards

    Stefan
  • sanketsanket Posts: 28
    edited 2009-10-25 06:17
    Hi all,
    i dont have a propeller chip.
    Actually, i am working on the propeller architecture.
    I am writing code for multi-core architecture and trying to increase the speed.
    I am really thankful to all you guys to have a wonderful support.

    Regards
    Sanket Shah
  • potatoheadpotatohead Posts: 10,261
    edited 2009-10-25 06:26
    ?!?

    You mean writing code for something like an FPGA, or just writing code, thinking it through for "more speed" in an idealized way?

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  • Cluso99Cluso99 Posts: 18,069
    edited 2009-10-25 06:28
    Just an addition to the info... The WC option must be specified in the instruction (otherwise the carry is not changed). As above, with WC, the carry is set if bit 31 of the destination register (cog memory address) which is really also the source of the data in question, but the source field contains either an immediate number of bits to shift left, or the cog address of the location of the value to shift left, is a "1" and reset if "0". This occurs, even if you specify the NR (no result = no write) option. So, we use the ROL with WC and NR to test bit 31 and set/reset the carry accordingly.

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  • sanketsanket Posts: 28
    edited 2009-10-26 06:23
    Not for FPGA. i am writing for propeller architecture.
    The concept of the Propeller is multi-core processor. So, I am writing code in VerilogHDL for the same using four stage pipeline.
    In case of speed, I am not designing HUB in round robin fashion in order to allow main memory access to cog.
    I am using other logic to increase the speed.

    Regards
    Sanket Shah
  • heaterheater Posts: 3,370
    edited 2009-10-26 09:20
    I'm confused.
    You are creating some kind of multi-core processor in Verilog but it is not for FPGA. So what then? All I can think is ASIC. Or is this only ever going to be runin simulation.

    Don't forget that the round robin HUB ensures deterministic timing of the execution of the COG code. Anything else maybe faster but does not have that important feature.

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  • sanketsanket Posts: 28
    edited 2009-10-30 10:40
    Hi,
    I think you are right.. Its for FPGA, but i had not thought anything about particular application.
    As i want to know you is, this is just my masters project.
    All i can say is that i am designing some kind of multi-core architecture (hardware design using verilog) which is to be synthesized.
    I understand your concept with round robin hub design. But, I am bounded by the design given by my advisor.
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