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xi xo traces for super prop — Parallax Forums

xi xo traces for super prop

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  • Toby SeckshundToby Seckshund Posts: 2,027
    edited 2009-09-12 21:19
    The prop does its own loading caps so too much extra would be bad, narrow tracks will help. The global clock pins of the CPLD might have a higher capacitance as it goes more places. There would be extra pickup or radiation from the lines but even 40mm shouldn't be too bad as long as it doesn't run parallel to a bad source of interferance.

    Do both the XI and XO pins have to go to the CPLD?? XI is the mot sensitive to interferance as it is the input to the OSC, XO is the output and presumably goes to the CPLD clock lines. Some discussions have shown the XI and XO pins of multiple props connected together, I would have thought that just the "master" prop's XO would have gone to the "slave" XI pins.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-12 21:33
    Well I am doing 102um traces so that will cut down capacitance.

    Interfearancd should be a small issue I have ground plane on both sides of trace and also on layer above trace. With data lines running perpendicular where they must cross.

    I can place a jumper disconnect between xi and cpld but can't on xo do to space shortage.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-12 21:48
    Also xi will not go to gclk. Xo will for cases where cpld is run off same clock xi will be general output for when prop cpld provides high speed clock.

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  • Cluso99Cluso99 Posts: 18,069
    edited 2009-09-13 01:55
    The xtal oscillator circuits have improved a great deal since they were originally placed internally into chips such as motorola, zilog and the like. These original circuits were extremely sensitive and were more trial and error than anything that could be published. Admittidly this has improved heaps.

    However, having said that, we know the prop is sensitive in this area, and the PLL can be killed. What you are doing is not permitted in the data sheet, so you are on your own here. Personally, I would not use this method.

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  • mctriviamctrivia Posts: 3,772
    edited 2009-09-13 02:44
    Neither would I but would it hurt to run the traces so others could program to use if they like or should I say this is not even an option.

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  • Cluso99Cluso99 Posts: 18,069
    edited 2009-09-13 02:55
    The traces could act like an aerial depending on the termination at the other end. In preference, don't place the tracks.

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    Links to other interesting threads:

    · Home of the MultiBladeProps: TriBlade,·RamBlade, RetroBlade,·TwinBlade,·SixBlade, website
    · Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
    · Prop Tools under Development or Completed (Index)
    · Emulators: Micros eg Altair, and Terminals eg VT100 (Index) ZiCog (Z80) , MoCog (6809)
    · Search the Propeller forums·(uses advanced Google search)
    My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
  • mctriviamctrivia Posts: 3,772
    edited 2009-09-13 03:03
    Thanks. I thinki will run the trace but end 102um short. Would make easy to hack if someone wants to but makes no physical contact.

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  • dMajodMajo Posts: 855
    edited 2009-09-13 11:46
    Cluso99 said...
    However, having said that, we know the prop is sensitive in this area, and the PLL can be killed. What you are doing is not permitted in the data sheet, so you are on your own here. Personally, I would not use this method.

    I think the PLL has been killed for other reasons (ESD, overvoltage ...) not because of the wrong capacitance on the oscillator's pins. Because of the enable/bypass options I think that there is at least one gate between the XO pin and the pll, and no connection to XI. The prop have adjustable capacitance inside.·Perhaps the oscillator will oscillate at slightly different frequency or in the worst case not oscillate at all but none of this will kill the pll.


    Anyway the purpose is to avoid the usage of the pll and to feed the prop with a clean frequency from DC to 80/100MHz.
    1) In this way the cpld will be always phase alligned with the prop system clock. (The pll, from its nature,·introduces random phase angles, within the clock period if good, but this is still a phase drift)
    2) This allows the prop being fed by a high accuracy frequency down to DC(156K) switchable on the fly (also by external events) allowing thus timing accuracy at low speeds and high speed reaction to events accomplishing big power savings.


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