Multiple SRAM chips on a PCB - A warning to the unwary

Cluso99

I see numerous comments about putting "lots" of 10nS SRAMs on a PCB connected to the prop.

At this speed (or even 50nS), track length, width and routing will play a huge part in the design, as will the chip loading (number of chips on the bus). There is likely to be ringing and cross-track interferance. Rise and fall times will also be important. Connections between multiple pcbs will be even worse.

To look at the waveforms you will require some very expensive equipment. Just the occasional glitch could cause problems with running programs.

Professional pcb designers have all sorts of tools and still PC motherboards go through many iterations before they are released (and have done so for years, even at 33MHz).

Please be careful not to waste money on flawed designs.

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Post Edited (Cluso99) : 8/15/2009 7:08:56 PM GMT

jazzed

The worst part is when a current hungry board blows up your PropPlug when it is connected and no external power is supplied [noparse]:)[/noparse]
The PropPlug allows current to flow through it IO pins to the Propeller and enough current will damage the FTDI chip.

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--Steve


Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230

Toby Seckshund

Most motherboards put "wiggles" into the paths to equalize the path lenths. Even on my Z80 boltings I have left pads to allow for some path dampers or terminations. The old 16KB 4116 chips had dampers at a couple of MHz and demanded vast arrays of decoupling.

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Style and grace : Nil point

heater

Z80 - Nah, we used to just wire-wrap everything and it just worked. Until things got stretched to three cards down the backplane, which was wire-wrapped as well.

Still I think our decoupling, caps stretched across the power pins, were better placed than on a lot of PCBs I've seen.

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For me, the past is not over yet.

Ale

Cluso:

Something I saw with my pPropQL020 board: The BUS capacity held the last written data even after some 125 ns . I had to issue 2 NOPS between write and read to reliably read the memory. If not I could read any non-existant position as if it had memory. Of course it would have not passed the unique data per address read after all the memory was written... but still would pass the read-after-write test .

I'm now doing a board for a Coldfire (coldfire+prop and maybe an XMOS) that I plan to use at maximum speed, some 50 MHz. Now that you mention it I may put some 33R resistors in the data/address BUS.

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MATH on the propeller propeller.wikispaces.com/MATH
pPropQL: propeller.wikispaces.com/pPropQL
pPropQL020: propeller.wikispaces.com/pPropQL020
OMU for the pPropQL/020 propeller.wikispaces.com/OMU

Toby Seckshund

Hey, don't you lessen my dream!

I still remember being able to out speed other SBCs with my 4MHz N1 ! And be able to marvel at this new fangled technology !

For me the past is still to happen.

I look too hard at problems even when they could be ignored, My father's fault ( bloody engineers ). Once he wascommisioned to help on a chemical treatment bed. It was about 10-12 baths of pickling solutions intermixed with washes for turbine rotor blades. When it cane to controling the transit system (pnumatic) I got up on my back legs and ventured the N1, got told to shut up as the eproms had a failure rete of 1 bit/KB per year (which was deemed too high for Mil purposes). I found out that the chosen device ended up as a PCB disk with contacts, like an LP on Valium.

Thirty years later ... the Prop would have beel Ideal.

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Style and grace : Nil point

Bill Henning

Hi Cluso99,

Good point - I will do some tests in a couple of weeks. I can now hook up enough hardware now as I have enough connectors.

I believe that everything will work fine at 20MHz burst rate with four boards using the DIP 32 chips; the maximum distance for a signal to travel is about 8" to the last chip on the last board. I was well aware of bus capacitance issues when I designed Morpheus and Mem+, and tried to account for it by using 8 mil traces and keeping traces as short as I reasonably could. I also made sure I only used gold plated connectors for MORPHBUS

As soon as I reflow some of the SOJ36DIP32 boards, I will try how fast I can go with just on-board memory, one Mem+, two, three and four!

That will be a fun series of tests... theoretically I may be able to hit 100MB/sec (yes, mega bytes per sec) using five cogs and fast memory - and if not, 50MB/sec would not be too bad... of course bus capacitance may limit the number of Mem+ boards at the higher speeds.

Now back to my regularly scheduled documentation writing....

Cluso99 said...
I see numerous comments about putting "lots" of 10nS SRAMs on a PCB connected to the prop.


At this speed (or even 50nS), track length, width and routing will play a huge part in the design, as will the chip loading (number of chips on the bus). There is likely to be ringing and cross-track interferance. Rise and fall times will also be important. Connections between multiple pcbs will be even worse.



To look at the waveforms you will require some very expensive equipment. Just the occasional glitch could cause problems with running programs.



Professional pcb designers have all sorts of tools and still PC motherboards go through many iterations before they are released (and have done so for years, even at 33MHz).



Please be careful not to waste money on flawed designs.

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Morpheus & Mem+dual Prop SBC w/ 512KB kit $119.95, 2MB memory IO board kit $89.95, both kits $189.95
www.mikronauts.com - my site 6.250MHz custom Crystals for running Propellers at 100MHz
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Post Edited (Bill Henning) : 8/15/2009 10:44:24 PM GMT

waltc

Good warning Cluso. I know I won't touch any Prop memory board until they've been out for a year or so. They are a far cry from designing and building memory for 8 mhz systems with 150ns memory reads and writes(I'm thinking about the old home brew memory expansion boards/solutions for the Atari ST and Amiga here).

heater

It was once put to me that one can have problems with high speed circuits even if the frequencies in use are very low.

Why so?

Those pico second fast edges required to get high frequencies are still pico second fast if delivering a signal of only 1Hz. So they can give rise to odd reflections, cross talk and glitches even when you think you are operating at a comfortably low frequency. Not to mention hammering on the power rails and decoupling caps.

For this reason FPGAs come equipped with programmable slew rates on their outputs.

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For me, the past is not over yet.

Toby Seckshund

That was what was worrying me on my board. It may have a chip on it which is marked Z80 ish but it is a higher speed CMOS version, talking to a few HC latches and buffers, and all this is driven from the props fast edges.

Overshoots will test those 0.5mA diodes. Are there any undershoot diodes on a Prop ?

Wasn't there a Josethson (something like this) junction computer that ran just up from absolute zero. it was said to have a max freq of 1GHz and had to be built within an eight inch cube because of path lenths.

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Style and grace : Nil point

Post Edited (Toby Seckshund) : 8/16/2009 10:32:18 AM GMT

waltc

Those pico second fast edges required to get high frequencies are still pico second fast if delivering a signal of only 1Hz. So they can give rise to odd reflections, cross talk and glitches even when you think you are operating at a comfortably low frequency. Not to mention hammering on the power rails and decoupling caps.


And even worse when you're designing and building memory boards that are coming close to PCI data rates.

Which is why I'll wait a year or so and see what happens to the early adopters of these home brew high speed memory boards.

jazzed

Well, at least the one enabled SRAM on an 8 bit bus with multiple capacitive loads will try to deliver the goods [noparse]:)[/noparse] If the slew rate is too fast and generates overshoot, it's a longer-term problem and will not show up as a problem right away unless the board is total junk. Shelving on clock or edge sensitive control lines is more critical short term.

Adding small series terminating resistors and correct bypass can help. Series terminations that are too big will of course cause other issues like someone mentioned. Super long traces should be avoided of course, and having good power and ground planes can help a lot.

Without a 1 GHz scope, tiny ground leads, and patience for doing Signal integrity Analysis (SA), the designer will never know what is being delivered. It's a key "Engineering" detail along the same line as "Root Cause Analysis."

Aside from signal integrity and possibly sucking too much power, there is not much to worry about. Fear, Uncertainty, and Doubt (FUD) rules where knowledge fails.

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--Steve


Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230