TI 12-bit DAC object (TLV5630)

ry.david

I have temporarily mocked up a TLV5630 on a breadboard and altered Beau Schwabe's AD8803 code to get it running.· Once I get the Spin code working properly, I am going to convert it into assembly and add it to the Object Exchange.

I do have one question though.· During updates, the channel seems to go low.· Unfortunatley, I did not have time to monitor FS and CLK on the same plot, but you can see that after 10ms the output goes low for ~1ms.·· This corresponds with my waitcnt(clkfreq/100 + cnt) between updates.· Am I missing something in the datasheet or have it wired wrong?· Attached is code, scope plots, datasheet, and schematic of how I have it wired currently.

Thanks!
Ryan

Timmoore

Couple of comments

1. The pre line is floating, if it is read as a low then it will force a 0 ouput - which maybe what you are seeing.
2. Outputing MSB first - it may be easier to reverse the bits (the >< operator) , e.g.

  temp := Address << 12 + Value
  temp ><= 16                                           ' MSB is now LSB

  repeat 16
    outa[noparse][[/noparse]DAC_DIN] := temp & 1                           ' clock out MSB first
    outa[noparse][[/noparse]DAC_CLK] := 1
    outa[noparse][[/noparse]DAC_CLK] := 0
    temp >>= 1

ry.david

Timmoore said...
Couple of comments

1. The pre line is floating, if it is read as a low then it will force a 0 ouput - which maybe what you are seeing.
2. Outputing MSB first - it may be easier to reverse the bits (the >< operator) , e.g.

Thanks a lot!

1.· I corrected the schematic and added a jumper on my breadboard.
2.· Your code is a lot cleaner...

I will access to a scope again tomorrow to check the output.

Thanks again!
Ryan

ry.david

Alright, here is a updated scope plot, with the new code and PRE pin, mentioned above.· It still goes low during updates, the channels on the scope are listed to the right of the signals.· Anyone have an idea why the output still would go low?

Thanks!
Ryan

Timmoore

I would try leaving sclk high when fs is high. There is stuff in the spec about sclk when fs is high an you holding sclk low maybe confusing it.

ry.david

Timmoore said...
I would try leaving sclk high when fs is high. There is stuff in the spec about sclk when fs is high an you holding sclk low maybe confusing it.

I had modifed the code to do this, through a init routine which handles setting up CLK, FS, and DIN before any setting.· I tried it out today on the scope with the same result.· I did however make a small discovery.· I was initially under the impression the LDAC pin was soley for loading preset values.· After reading the datasheet for the 100th time today, it looks like the LDAC pin must be pulled high while clocking in data.··My thinking is that once each register is being written to, the output is immediatley latched.· Pulling LDAC high SHOULD·prevent latching of the output until it is pulled low again.

If anyone is interested, I can update code and test this.· If I am correct, this DAC would require 4 propeller pins (unless maybe you could drive LDAC on a inverted FS?) and my end application already has used all available pins.· I am switching over to the TI DAC7568 which actually I think may work out for the better (smaller footprint, and a little cheaper).

Timothy D. Swieter

I am interested in learning more about this object once I get time for a future project.

I just love the forums, the "><" command wasn't in my programming vocab. Now it is - thanks Timmoore.

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Timothy D. Swieter, E.I.
www.brilldea.com - Prop Blade, LED Painter, RGB LEDs, 3.0" LCD Composite video display, eProto for SunSPOT
www.tdswieter.com