Dealing with the sleep glitch
photomankc
Posts: 943
I have the code for my first project pretty well complete but had one issue come up that is bugging me still although not pressing anymore. The basic idea is a universal USB charger that runs on 6AA NiMH batteries and provides a 5V ~400mA output via USB as a convenience device when I don't want to bust out wall wart chargers or we are camping, etc. The stamp is there to provide:
- Voltage monitoring and feedback via three LEDs that lindicate charge when a button is pressed.
- Delayed shutdown interface using the LEDs to provide three different timeouts to prevent battery depletion by devices that never stop charging and the regulator
- Shut the entire regulator down and sleep when the pack voltage hits 6.1V under load to prevent deep discharge of the batteries.
All my basic functions are working but I ran into one snag that got me curious. I use an NPN power transistor to control the load and let the Stamp cut of the load when needed. I used a 1.5K resistor from the stamp to the transistor to limit base current but try to also keep it saturated. Higher values seemed to produce a pulsation in the regulator's LED and my IPod did not like that at all. My original idea was to NAP wherever possible for delays to reduce power consuption of the already loss ridden regulator circuit. However if I tied the transistor base high with a resistor value small enough to keep it 'on' when the sleep glitch appeared on the output from the stamp, when it came time to shutdown and END the stamp program the transistor would pulse on at each watchdog wake-up of the Stamp and it was enough to keep pulsing the charging loads on and off... not good. If I tie it low, then the opposite happens and any NAPS in the Stamps main loop cause the transistor to pulse towards off and thus keep triggering charging devices to think they were disconnected and reconnected. Not good either.
Ultimately my time-delay circuit and the loop-counting method of timing it uses in absence of any time keeping in the Stamp require me to not use NAP anyway. The variation in timing with NAP throws everything off and can accumulate some big errors over the 1 and 3 hour auto-off timer durations. I left the base of the transistor floating and that seems to work the best of everything else, but with no NAPs in the main loop now I could probably tie it low to help keep it stable. But my question still remains. What's the easiest way to keep that glitch from causing outputs you need held in certain, non-default, state by the Stamp from pulsing? I thought maybe a latch of some kind but that adds another DIP to the final product and I don't want to do that. Just curious if others have run into this and have a solution for future reference.
A programmable USB charger! Totally impractical and yet still so cool!
- Voltage monitoring and feedback via three LEDs that lindicate charge when a button is pressed.
- Delayed shutdown interface using the LEDs to provide three different timeouts to prevent battery depletion by devices that never stop charging and the regulator
- Shut the entire regulator down and sleep when the pack voltage hits 6.1V under load to prevent deep discharge of the batteries.
All my basic functions are working but I ran into one snag that got me curious. I use an NPN power transistor to control the load and let the Stamp cut of the load when needed. I used a 1.5K resistor from the stamp to the transistor to limit base current but try to also keep it saturated. Higher values seemed to produce a pulsation in the regulator's LED and my IPod did not like that at all. My original idea was to NAP wherever possible for delays to reduce power consuption of the already loss ridden regulator circuit. However if I tied the transistor base high with a resistor value small enough to keep it 'on' when the sleep glitch appeared on the output from the stamp, when it came time to shutdown and END the stamp program the transistor would pulse on at each watchdog wake-up of the Stamp and it was enough to keep pulsing the charging loads on and off... not good. If I tie it low, then the opposite happens and any NAPS in the Stamps main loop cause the transistor to pulse towards off and thus keep triggering charging devices to think they were disconnected and reconnected. Not good either.
Ultimately my time-delay circuit and the loop-counting method of timing it uses in absence of any time keeping in the Stamp require me to not use NAP anyway. The variation in timing with NAP throws everything off and can accumulate some big errors over the 1 and 3 hour auto-off timer durations. I left the base of the transistor floating and that seems to work the best of everything else, but with no NAPs in the main loop now I could probably tie it low to help keep it stable. But my question still remains. What's the easiest way to keep that glitch from causing outputs you need held in certain, non-default, state by the Stamp from pulsing? I thought maybe a latch of some kind but that adds another DIP to the final product and I don't want to do that. Just curious if others have run into this and have a solution for future reference.
A programmable USB charger! Totally impractical and yet still so cool!
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Tracy Allen
www.emesystems.com