[HX512] custom firmwares
kuroneko
Posts: 3,623
I had the chance to verify my f/w designs this week (ISP cable arrived), so I thought I might as well share them in case they prove useful to others.
Unless stated otherwise the CPLD retains the pin assignment used by the Hydra (clock/reset/command) as well as the command encoding (rd/wr/latch). The archives contain the ABEL source file(s) and the JEDEC file for 3.3V/slow slew rate.
Unless stated otherwise the CPLD retains the pin assignment used by the Hydra (clock/reset/command) as well as the command encoding (rd/wr/latch). The archives contain the ABEL source file(s) and the JEDEC file for 3.3V/slow slew rate.
hx512_cpld.0 - no setup cycle (hard-wired post-increment) - no part of the address is p/reset while setting any other part - commands: %0-: rd/wr %10: latch LSB (1 cycle) [b]LSB[/b] %11: latch MSB (1 cycle + 1 optional cycle to set 64K page) [b]MSB [noparse][[/noparse]page][/b] - LED assignment: P5/-/-/P2..P0: latch mode/-/-/page
hx512_cpld.1 - no setup cycle (hard-wired post-increment) - no part of the address is p/reset while setting any other part - commands: %0-: rd/wr %10: latch LSB (1 cycle + 2 optional cycles to set MSB and page) [b]LSB [noparse][[/noparse]MSB [noparse][[/noparse]page]][/b] %11: latch MSB (1 cycle + 1 optional cycle to set 64K page) [b]MSB [noparse][[/noparse]page][/b] - LED assignment: P5..P4/-/P2..P0: latch mode/-/page
Comments
I know this sounds vague, but I would rather not invest in the cabling, verification, and whatnot. I send the card to you and you send the card back reprogrammed. Just think about it.
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JMH
@all: Is there someone closer (locationwise) to James who could help him out?
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
http://hobby_elec.piclist.com/e_cpld3_3.htm
Ron
The intellectual challenges very simple I just do not have time.
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JMH