Sigma Delta ADC - How is AC sampling handled?

Kye

So, I've studied how the Sigma Delta ADC works for a while now and I think I have a pretty good handle on how it works and how to use it on the propeller chip. However, I don't fully understand how it can handle AC voltages or more specifically, negative voltages.

For example, if I am sampling a +-1vrms signal, how can the propeller chip sample the -1vrms side of the signal?

I'm using the standard circuit given by the counter app note:

                          ''       3.3V
                          ''       
                          ''       │
                          ''      1nF
                          ''       │
  ADC_Feed_In_Pin   = 5   '' ─────┫  0.1uF
                          ''   100K┣─── Mono In
  ADC_Feed_Back_Pin = 4   '' ───┫
                          ''       │
                          ''      1nF
                          ''       │
                          ''       

Do the 1nF farad capacitors provide some type of dc offset to the signal? I really am quite sketchy on what they are for and how the 100K resistor plays into the circuit. I understand the whole idea behind the sigma delta·Adc and how the propeller chip's counters are used to act like a sigma delta adc, but I'm not quite sure on what all·the analog parts·are doing...

Anyone know how it samples AC voltage? Because the counters only work by accumulating a register, making it hard for it to sample something in the negative realm since that would require it to decrement the register. Thus the propeller chip can only sample a positive voltage...

Thanks, for your help,

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Nyamekye,

Beau Schwabe

Kye,

The whole concept of the Sigma Delta ADC is to keep the voltage to the input pin right at the pin threshold that it changes from a 1 to a 0. The Feedback resistor in combination with the power rail caps help to keep this in check. In the case of the Propeller the threshold is "close" to Vdd/2, so if you supply an external voltage that's right at Vdd/2 then it would make sense that the ratio of 1's to 0's should be right at 50%. If the external voltage is closer to Vdd then the ratio of 1's would be higher, likewise, if the external voltage is closer to Vss, then the ratio of 0's would be higher. So far everything I have mentioned refers to a DC level on the input between Vdd and Vss. By introducing a cap on the input you can measure AC signals. The cap creates a DC bias within the cap which causes any +AC voltage to persuade the input closer to Vdd, while any -AC voltage will persuade the input closer to Vss. The feedback resistor in combination with a series input resistor form a voltage divider. Note: Input resistor used if DC voltage is expected to be greater than Vdd or if the AC voltage is expected to be greater than +-Vdd/2.

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Beau Schwabe

IC Layout Engineer
Parallax, Inc.

Kye

Oh, okay, I understand now what to do. (Still not sure on why a capacitor creates a DC bias, I thought caps removed dc bias).

So, if I were measuring a 1vrms audio signal I would not need an input resistor.

So then, if the signal were under a certain threshold, lets say vdd/2 it would be negative and if it were over this threshold it would be positive.

I can then just subtract the (2^(number of bits - 1) ) from the resulting value to center the sampled value arround zero.

Since I'm sampling at 44100 khz I'll need to play with the value returned from the PHSA register first before I can apply this scaling to move it out of the percentage territory since I'm not reading a sample every 2^power cycles.

So then equation for the percentage would be...

(1 / (cyclesWaited / bitsOfResolution) ) - Which would yield the number the input needs to be scaled by for the value to occupy said number of bits of resoltuion. This would throw away a bit of accuracy however.

Then I just center the value arround zero and I am finished.

To bad I can't get 16 bits at 44100 khz, I would have really liked that. However, I'll just scale up a value sampled with 11 bits of resoltution and call it a day.

Thank you,

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Nyamekye,

Leon

If you put a negative charge on one plate of a capacitor, you will get a positive charge on the other plate.

Leon

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Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle

Beau Schwabe

Kye,

The "DC bias" is within the cap, thus allowing it to block DC and pass AC as long as the AC does not try to go above 1.65V or Below -1.65V. The AC that is passed gets "summed" into the Vdd/2 threshold, so a negative voltage will pull closer to Vss, while a positive voltage will pull more towards Vdd.

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Beau Schwabe

IC Layout Engineer
Parallax, Inc.