Using a counter to serialize reading bits?
lonesock
Posts: 917
Hi, All.
I need some feedback on this idea:
OK, say I want to have a really fast SPI interface: I know I can set up a counter to act as my clock, then to read in a byte, do 8 of the following:
Now, I'm greedy, so I want to go twice as fast. Here's the plan:
1) set up CTRB to act as my clock, output on the SCK pin (don't start it yet)
2) set up CTRA in POS detector mode, where pin A is my SDI pin, and set FRQA to 1<<7, and PHSA to 0 (don't start it yet)
then start CTRA, then CTRB, then do the following 8 times:
Now shut down both counters, and my desired value should be in the low 8 bits of PHSA.
Would this work? I'm not sure about the order I should start Counters A and B, or the phase of the clock line relative to the actual read (the POS detector mode specifies that it reads the APIN delayed by 1 clock). Any feedback from the local gurus?
thanks,
Jonathan
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lonesock
Piranha are people too.
I need some feedback on this idea:
OK, say I want to have a really fast SPI interface: I know I can set up a counter to act as my clock, then to read in a byte, do 8 of the following:
test mask, ina wc rcl data, #1
Now, I'm greedy, so I want to go twice as fast. Here's the plan:
1) set up CTRB to act as my clock, output on the SCK pin (don't start it yet)
2) set up CTRA in POS detector mode, where pin A is my SDI pin, and set FRQA to 1<<7, and PHSA to 0 (don't start it yet)
then start CTRA, then CTRB, then do the following 8 times:
shr FRQA, #1
Now shut down both counters, and my desired value should be in the low 8 bits of PHSA.
Would this work? I'm not sure about the order I should start Counters A and B, or the phase of the clock line relative to the actual read (the POS detector mode specifies that it reads the APIN delayed by 1 clock). Any feedback from the local gurus?
thanks,
Jonathan
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lonesock
Piranha are people too.
Comments
Hee hee! That's pretty clever! One problem is that you'll get four counts for each "1" bit (four clocks per instruction). So you'll have to shift the value from PHSB right by two after you read it. (You can't shift PHSB itself.) If you can't get the two counters to synchronize just right, you can always externally AND the SCK and SDA lines and count edges with CTRA instead of levels.
-Phil
edit: Great point about just correcting it via dividing by four after the fact!
edit2: I see, the PLLDIV only works in a PLL counter mode...oops
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lonesock
Piranha are people too.
Post Edited (lonesock) : 6/1/2009 5:40:51 PM GMT
My feeling, on second thought, is that this would be unreliable, since it depends on a precise relationship between the edges of SDA and when ina is sampled by ctra. I'd be much more inclined to use the external logic and count edges.
-Phil
1) it means I only have to divide by 2 at the end
2) I'm not reading the SDI pin while the value is changing (depending on the SPI mode, of course)
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lonesock
Piranha are people too.
-Phil
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lonesock
Piranha are people too.