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Can 2 Basic Stamps be I2C masters controlling the same slave? — Parallax Forums

Can 2 Basic Stamps be I2C masters controlling the same slave?

modemmanmodemman Posts: 41
edited 2009-05-31 22:12 in BASIC Stamp
Hi,

I upgraded to a BS2PX and had an old BS2P laying around so I decided to add the old BS2P to my bot and use it to outsource non-critical tasks, such as speech and other "fun" or cosmetic tasks (blinking lights, output to LCD, etc.) to free the main Stamp to do stuff that relies on speed, such as reading various sensors and updating all the servo pulses.

I hooked up the 2 stamps as described in www.parallax.com/Portals/0/Downloads/docs/prod/stamps/web-BSM-v2.2.pdf under the SERIN command (page 410 in my version). For the longest time I considered this to be some dark ancient art and had to study humanoido's projects to figure it out, but then of course, as usual, it was right there, under my nose, in the manual... Anyway, made that work, but there's a catch:

Because there's no buffer, the transmitting Stamp has to transmit for a while, until the receiving Stamp gets the message, and, the receiving Stamp has to constantly listen in order not to miss the message. That makes things kind of sluggish, and only works well for those who are versed in the dark art of subsumption programming.

So I came up with this idea, but I paid too much for my Stamps (wish I knew about the recent $50 sale...) to blindly experiment with them, so I need your kind expertise:

Is is possible to hook up both Stamps to one Eeprom chip (same chip) via I2C to do the following (basically act as a simple buffer):

The main Stamp sends a command to the Eeprom (just some text string) and changes a "trigger" bit from "0" to "1", then immediately goes about its business. The secondary Stamp, checks the "trigger" bit on the Eeprom at pre-programmed intervals, or whenever it's done doing whatever it was doing. Then, if it sees that the "trigger" was tripped to "1", read the command stored in the Eeprom and execute it. I suppose, in a further step, it would be even possible to construct a FIFO queue of sorts, maybe even with priorities, so if there are 3 commands waiting in a queue, but only one is very important (for example, one needs to update a sensor status on an LCD, the other 2 just speak funny stuff, the status update takes priority), the other 2 are either discarded or moved to the end.

I guess my long(ish) question can be broken into pieces:

1. Is it possible to have 2 masters (I know the Stamp cannot be a slave) on the same I2C line.

2. If 1 is yes, what is the correct way to physically wire this up.

As always, thanks for your kind guidance.

modemman

Comments

  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2009-05-29 16:48
    The BASIC Stamp I2C protocol does not support multi-master bus configurations. Do you want to buffer just single eight-bit commands, or do you need to buffer multi-byte strings?

    -Phil
  • modemmanmodemman Posts: 41
    edited 2009-05-29 17:25
    Phil, thanks for replying. Got it re: multi-master.

    Single 8 bit commands should be sufficient.

    Thanks.

    modemman
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2009-05-29 17:43
    I've got an idea how to do this simply. Can you get by with a 6-bit command?

    -Phil
  • modemmanmodemman Posts: 41
    edited 2009-05-29 17:54
    6 bit is what... 64 possibilities... sure! Anything is better than nothing.

    Thanks Phil.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2009-05-29 21:01
    modemman,

    Here is a circuit (untested) that should work for you. Resistor values in the neighborhood of 4.7K should work fine here:

    attachment.php?attachmentid=61237

    It works like this:

    1. The slave tristates RCVCLK then pulses the /ACKIN pin low to clear the shift regster.

    2. Whenever the master (left side) wants to send a command to the slave (right side), it embeds the 6-bit command between "1" bits (%1cccccc1) and sends it via SHIFTOUT, using the XMTCLK and XMTDAT lines. Then it leaves XMTCLK low, and tristates XMTDAT.

    3. The slave, once it sees a "1" bit on RCVDAT, knows that a command is in the shift register ready to be clocked in; so it uses RCVCLK and RCVDAT to do that, using SHIFTIN. While it's doing this, QA keeps getting fed back to XMTDAT. Since it was a "1", it remains a "1".

    4. Go back to step 1. This immediately clears QA and QH, which tells the master that the slave received the data, and tells the slave that there's no new data in the shift register.

    -Phil

    Post Edited (Phil Pilgrim (PhiPi)) : 5/29/2009 9:07:13 PM GMT
    494 x 333 - 3K
  • modemmanmodemman Posts: 41
    edited 2009-05-30 13:55
    That's a pretty awesome idea Phil! I'm heading to digikey right now and will definitely test this. That's what they use in making LCD screens serial, shift registers, right?

    Thanks.

    modemman
  • Tracy AllenTracy Allen Posts: 6,662
    edited 2009-05-30 19:59
    mmm. I wouldn't discard the multi-master idea entirely. The I2C buss is wired OR, so first one Stamp and then the other could access the same I2C slave, so long as they don't try to do so at the same time. (==> flow control or collision detection) For the original idea, something like an RTC chip with built in RAM would be better than an EEPROM, which has a limited number of write cycles.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Tracy Allen
    www.emesystems.com
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2009-05-30 20:44
    Tracy,

    Hmm, yes, a multi-master system would work with the Stamp if a flow control scheme were implemented with extra Stamp pins or with an I/O pin on the slave device itself, which could be set and cleared. I'm trying to imagine how collision would work, though, since the PBASIC firmware is not designed to support it.

    -Phil
  • HumanoidoHumanoido Posts: 5,770
    edited 2009-05-30 20:44
    modemman said...
    The main Stamp sends a command to the Eeprom (just some text string) and changes a "trigger" bit from "0" to "1", then immediately goes about its business. The secondary Stamp, checks the "trigger" bit on the Eeprom at pre-programmed intervals, or whenever it's done doing whatever it was doing. Then, if it sees that the "trigger" was tripped to "1", read the command stored in the Eeprom and execute it. I suppose, in a further step, it would be even possible to construct a FIFO queue of sorts, maybe even with priorities, so if there are 3 commands waiting in a queue, but only one is very important (for example, one needs to update a sensor status on an LCD, the other 2 just speak funny stuff, the status update takes priority), the other 2 are either discarded or moved to the end.
    You could do this with a single wire and a "Stamp Listener." This is one stamp outpost that can receive and store the commands in EEPROM, and dish out the commands as needed. It's a simple matter to access the Stamp Listener and retrieve the data. The stamp has multiple pages/EEPROM and read write commands to do the trick. When using Stamp Outposts, there is no need to build a circuit or add chips. It's easy to set triggers and flags using the ports too.

    humanoido

    Post Edited (humanoido) : 5/30/2009 8:50:09 PM GMT
  • Tracy AllenTracy Allen Posts: 6,662
    edited 2009-05-31 22:12
    @modemman, In rereading your original message, I was wondering if you used the flow control options of SERIN and SEROUT? It was this comment that made me wonder:

    >>the receiving Stamp has to constantly listen in order not to miss the message.
    >>That makes things kind of sluggish, and only works well for those who are
    >> versed in the dark art of subsumption programming.

    It is not for all purposes. But flow control options along with timeouts of a little as one millisecond can make things a lot less sluggish when two Stamps talk.

    ▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
    Tracy Allen
    www.emesystems.com
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