PropXMM-D40 Module - Up to 1MB 5.0MB/s random > 5.33MB/s burst? SRAM
jazzed
Posts: 11,803
PropXMM-D40 allows a Propeller to access up to 1MB of SRAM accessible at 5.3MB/s on a carrier board using 16 pins. Each PropXMM-D40 will have 512KB of random access, byte wide Propeller expansion memory.
The DIP40 form factor allows a simple plug-in upgrade to current DIP40 Propeller boards with pins P0..15 free. The same board can be configured for a vertical 20 pin "SIP" form factor using a right angle header.
512KB SRAM available per module; two modules can be used with different address configurations for 1MB.
Spin/PASM code will need 2 COGs for full speed access and 1 COG for lower data rates.
Initial Projection: Access Rates (no overhead) 1. Byte > 2.2MB/s, 2. Word ~ 3.3MB/s, 3. Long > 4.2MB/s with 1 COG ~ 5.3MB/s 2 COGs.
6/01/09 Update: Access rates are TBD. More setup overhead is required than initially budgeted.
6/02/09 Update: Now doing 5.0MB/s random read and write. Focusing on verifying 1MB address range and writing XMM C demo code now. PropXMM512-D40-9.zip also appears to work with 50ns SRAM. Added hand wired prototype pictures below. First PCB FABs are due next week.
6/06/09 Update: Finally, C XMM is running with the D40 prototype hardware with 1 COG same as my last prototype.
6/18/09 Update: FirstFab Protos are here. SIP concept shown below. DIP40 pin holes too small for preferred mechanical interconnects. One solution picture is attached.
Pinout:
The DIP40 form factor allows a simple plug-in upgrade to current DIP40 Propeller boards with pins P0..15 free. The same board can be configured for a vertical 20 pin "SIP" form factor using a right angle header.
512KB SRAM available per module; two modules can be used with different address configurations for 1MB.
Spin/PASM code will need 2 COGs for full speed access and 1 COG for lower data rates.
Initial Projection: Access Rates (no overhead) 1. Byte > 2.2MB/s, 2. Word ~ 3.3MB/s, 3. Long > 4.2MB/s with 1 COG ~ 5.3MB/s 2 COGs.
6/01/09 Update: Access rates are TBD. More setup overhead is required than initially budgeted.
6/02/09 Update: Now doing 5.0MB/s random read and write. Focusing on verifying 1MB address range and writing XMM C demo code now. PropXMM512-D40-9.zip also appears to work with 50ns SRAM. Added hand wired prototype pictures below. First PCB FABs are due next week.
6/06/09 Update: Finally, C XMM is running with the D40 prototype hardware with 1 COG same as my last prototype.
6/18/09 Update: FirstFab Protos are here. SIP concept shown below. DIP40 pin holes too small for preferred mechanical interconnects. One solution picture is attached.
Pinout:
- P0..7 Data and multiplexed address pins 1 - 8
- P8..13 multiplexed and direct address pins 13 - 18
- P14 14 bits address "latch" ALE pin 19
- P15 Write Enable WE pin 20
- VDD pin 12,32
- VSS pin 9,29
NC .. pins 10, 11, 21 - 28, 30, 31, 33 - 40
- Mainly XMM where code is fetched 4 to 64 bytes at a time (1 to 16 longs)
- External memory buffer
- Not optimized for emulations
- Targeted for PPDB, PropStick, SpinStudio, and GG boards without wires.
- Usable on PropDemo board solderless breadboard.
- Useful on PropProto or any P0..15 free board with wiring.
- DIP40 socket carrier board.
- SIP20 with right angle header.
- Dimension ~ 2.1" x 0.9" (53mm x 23mm)
Comments
PropXMM-D40-8.zip is a Spin/PASM demo for random long read·and write at 3.8MB/s and 4.2MB/s.
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
Post Edited (jazzed) : 6/2/2009 10:09:22 PM GMT
I think a lot of people will like it. I also use the '574's, nice latches.
Bill
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Largos - a nano operating system for the Propeller
www.mikronauts.com - a new blog about microcontrollers
I just thought of something... if you use P15 for ALE, you can use P14 for both WR and for an extra address bit for one of the latches; that way you could potentially have 2MB of ram.
Bill
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Largos - a nano operating system for the Propeller
www.mikronauts.com - a new blog about microcontrollers
I suppose you could do that if WE is on the output side of the latch ... I'll have to think about it when I'm fresh. BTW, let me know if you need a prototype of this for LMM/XMM and Largos. I have a small number of these coming in a few weeks.
@mikedev,
You could wire-wrap a similar circuit with DIP parts and sockets. I'm doing something similar with different parts just for code development until my prototypes come. My hand-built rats-nest development board will be slower since the 512KB SRAM DIP I'm using is 5V only and has slower access time (the assembled FAB I posted will not have such crazy caveats).... If you like, I'll post a schematic, part-list, and netlist that matches what I'm doing.
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
I am impressed. This is just what I needed for an Idea I have. I will let you know more about it soon.... hint: 16 pins is the key.
With that bandwidth, we could do qvga at 8b/p and 60 frames/second!
I have a curious question though. Why is the data p0 through p7 not lined up with IO0 through IO7?
Post Edited (hinv) : 5/29/2009 1:51:50 AM GMT
Would be great to see QVGA on a Propeller [noparse]:)[/noparse]
The data bits numbers are not the same so that I could connect everything on a DIP40 footprint board. You will notice some odd address lines numbering also for the same reason. For SRAM bit connection order doesn't matter. If the target board size was bigger, the bits could be easily aligned.
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
You see, when you assert ALE, the value of P14 at that time will be latched - as long as you make sure that WE is not active when ALE is, you won't have accidental writes.
Thank you for your kind offer, I'll PM you.... are you coming to the expo?
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Largos - a nano operating system for the Propeller
www.mikronauts.com - a new blog about microcontrollers
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
I'll be giving a talk on LMM & Largos &... and I'll have a couple of products too [noparse]:)[/noparse]
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Largos - a nano operating system for the Propeller
www.mikronauts.com - a new blog about microcontrollers
While trying to achieve similar objectives for slightly different purposes, we are approaching it from a different perspective. It will be interesting to see how both methods shape up and I am sure everyone will benefit. At the end of the day there will be concepts we both can benefit from.
Sure you cannot get your boards ready for the Expo???
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Links to other interesting threads:
· Home of the MultiBladeProps: TriBladeProp, SixBladeProp, website (Multiple propeller pcbs)
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: Micros eg Altair, and Terminals eg VT100 (Index)
· Search the Propeller forums (via Google)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
For C, usually the code does sequential fetching for 5-10 longs, and then a branch to a different addresses. So not totally random, but not block burst either.
It would be cool to have XMM ImageCraft C demo at the expo...
// richard
Post Edited (ImageCraft) : 5/29/2009 5:16:48 AM GMT
Thanks and yes I agree the free market of ideas is working in this case. I can't wait to see what Bill has to offer [noparse]:)[/noparse]
All it takes is money and 2-3 weeks to have product in hand if I think the demand justifies the quick-turn cost.
Richard,
Theoretically, a 16 long block read would be closer to 7MB/s raw throughput with two COGS.
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
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http://www.propgfx.co.uk/forum/·home of the PropGFX Lite
·
If you are going to offer the boards for sale as well I would be happy to buy a few from you , fair is fair and I am sure everyone else appreciates the contributions from guys like you and others
I love to come here and being able to download software/hardware that you guys make available since I found this site I have been going crazy buying parallax stuff and can say with certainly
I would not have spent the money I have if it were not for all the free stuff everyone shares here. With all my Freescale and PIC stuff I have lots there was never the support like there is here
Didn't mean to ramble but thought you guys should know how important it is to us newbies to be able to have access to so much information and support
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
My RamBlade is 1.96x1.0". The 1.96" is dictated by the TwinBlade because it is designed to fit into a box, and the panelisation requires one side to be constant due to V-Groove. Panel is 14.6x16.6".
Looking at your design, 1.96 is not achievable. What about 2.1x1.0"?
If so, maybe we could share half the panel and share the pcb costs??? My TwinBlade is not ready though my RamBlade is. Only problem is I use Protel v3 but can convert from v2.
Just not sure if there is enough demand for 56 pcbs of each to justify the costs.
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Links to other interesting threads:
· Home of the MultiBladeProps: TriBladeProp, SixBladeProp, website (Multiple propeller pcbs)
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: Micros eg Altair, and Terminals eg VT100 (Index)
· Search the Propeller forums (via Google)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
Post Edited (Cluso99) : 5/30/2009 3:31:34 AM GMT
At the end of the day, both solutions will end up using two Props. What’s the point of having 512k or 1meg of ram if we don’t have the cogs to drive the peripherals.
Both look like great solutions for Xmem, but do we really need two.
@jazzed
Not sure if should have started a new thread for this? Will move it if you wish.
Ron
Post Edited (Ron Sutcliffe) : 5/30/2009 5:34:11 AM GMT
Thanks for your panelizing offer. I would like to keep the width of the XMM-D40 at 0.9" or less.
I have more work to do before I commit to many boards though·... almost there.
Ron, I think there is a place for multiple designs. A project's goals should dictate the solution.
I'm open to a new thread of discussion on external memory ... it's a lively topic.
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
As I said above, our designs are based on different requirements. His design is using latches to save pins so that other things can be done. My design is non-latched and therefore uses all pins for SRAM and SD requiring it's own propeller. Each could become a standard in their own right, but they are too different for a standard between them.
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Links to other interesting threads:
· Home of the MultiBladeProps: TriBladeProp, SixBladeProp, website (Multiple propeller pcbs)
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: Micros eg Altair, and Terminals eg VT100 (Index)
· Search the Propeller forums (via Google)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
Really, well I’m not convinced in this case. There is nothing special about both boards, it is pretty straight forward stuff (sorry I am just looking at some exam papers for 3 year electronic trades students, Stathfield Tech, NSW). The difference now from the time Paul posted the original memXpand boards are the drivers, which you, along with many others have, brought to this forum.
@ Steve
If I recall you was one of those who argued strongly for some standards. If ever they were needed its now.
When its finished PM me and I will gladly purchase one from you too. I need it for XMM C [noparse]:)[/noparse]
Ron
BTW: My latching on the TriBlade Blade #1 SRAM uses the address lines to latch the upper address bits. Previous microprocessor designs with multiplexed data and address lines use the data lines to latch the extra address bits. The reason I use the address lines to latch the upper address bits is that I do not have to change the direction of the data pins to do this, which saves instructions and hence significantly improves speed.
Do you remember NetComm and SimpleComputing (SimpleModems)?
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Links to other interesting threads:
· Home of the MultiBladeProps: TriBladeProp, SixBladeProp, website (Multiple propeller pcbs)
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: Micros eg Altair, and Terminals eg VT100 (Index)
· Search the Propeller forums (via Google)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
Post Edited (Cluso99) : 5/30/2009 10:30:08 AM GMT
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
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Links to other interesting threads:
· Home of the MultiBladeProps: TriBladeProp, SixBladeProp, website (Multiple propeller pcbs)
· Single Board Computer:·3 Propeller ICs·and a·TriBladeProp board (ZiCog Z80 Emulator)
· Prop Tools under Development or Completed (Index)
· Emulators: Micros eg Altair, and Terminals eg VT100 (Index)
· Search the Propeller forums (via Google)
My cruising website is: ·www.bluemagic.biz·· MultiBladeProp is: www.bluemagic.biz/cluso.htm
I'm short of my per-long read data rate goal of 4.2MB/s as mentioned in the first post. Long write is fine for 4.2MB/s.
Bursting may still make 5.3MB/s .... I'm not sure. We'll see. I've posted a limited demo in the thread's second post.
The hardware design has to change. Using resistors to isolate the Propeller pins and SRAM data pins just won't work.
Instead I'm having to use my address latch signal as a chip select ... (would prefer this as output enable since it
simplifies the high address selection). Using a latch vs clock edge of course requires octal latches 74*573 variety.
My protoboard uses 74*373 for now.
Mikediv, I'm sorry I've had to delay posting a wire-wrap schematic and net list for you. I'm not sure when I can get to it.
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
More optimization might be achievable with other suggested code. The differences between v8 and v9 are address increment cog routine start timing, and using "the lonesock optimization" which I totally forgot about.
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
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JMH
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JMH
@JMH, The rates I presented are calculated and measured 5.0MB/s raw throughput from the PASM routines' first "andn dira, cs_ale" through the return instruction for use with XMM/LMM kernel ... actual LMM Instructions Per Second (LIPS) may be lower than data-rate/4 because of LMM interpreter processing rates for random read access. Cached LMM LIPS should average higher than data-rate/4, but I don't have an example to study yet. YMWV (your milage will vary) with overhead required for other applications.
I plan to use 74LCT573 on the production boards (574s are timing marginal with shared data/address bits). 74HC parts AC parametrics are too long at lower supply voltages.
Added: I forgot to mention this before, but I think I can·also achieve 5.0MB/s random long read using 1 COG with CTRA/CTRB driving address bits A0 and A1. Random long write rate will be lower though. CTRA/B driving bits A0 and A1 cost more than just incrementing the address. Random long write rate is lower than read.
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
Post Edited (jazzed) : 6/4/2009 12:47:40 AM GMT