Odd interrupt behaviour

Wayne G

Does anyone know of any known bugs in the SX48 interrupt system as i'm experiencing some odd behaviour.

By accident I caused a situation which I can't explain and now I would like to understand what is happening.

All my PortB pins are set for falling edge capture (schmitt trigger on) and only B.0 & B.3 are enabled for MWIU.·

MOV M, #$0A
CLR W
MOV !RB, W

MOV M, #$09
CLR W
MOV !RB, W

MOV M, W
MOV W, #%11110110
MOV !RB, W

·Then the interrupt routine goes as follows:

MOV M, #$9
CLR W
MOV !RB, W
AND W, #%00000011
ADD PC, W
RETI
JMP INPUT1_INT
JMP INPUT2_INT
RETI
RETI
RETI
etc

If you haven't noticed the mistake it was to enable the wrong PortB input, it should have been B.0 & B.1

Now the odd behaviour is that if I momentarily ground B.1 as you would expect nothing immediately happens however if I then momentarily ground B.3 the interrupt routine associated with B.1 activates even though the·MWIU for that input has·not been selected.·

Somehow the value of B.1 appears to be·stored in WKPND_B·even though it is not an interrupt and when when the B.3 interrupt is processed the AND function leaves the result of B.1 which·activates the INPUT2_INT interrupt.

I have checked the hardware and there is not an issue also there can be any amount of time between the grounding of B.1 & B.3 so long and they are grounded consecutively in the order B.1 --> B.3.

Any thoughts or ideas would be appreciated.

Thanks

Wayne

Phil Pilgrim (PhiPi)

This is the normal behavior. The wakeup pending register captures the selected edges for all pins, even if their respective interrupts are not enabled. This allows the programmer to use the edge capture facility in polled as well as interrupt modes of operation. The obvious solution is for the interrupt routine to test only those pins which have been interrupt-enabled.

-Phil

Wayne G

Thanks Phil

Can you point me to where in the manual this is mentioned.· I have read and re read the documentation and have not seen anything about this however·I did suspect it·was happening.



Wayne

Phil Pilgrim (PhiPi)

In Figure 7-1, you will notice that the port B pin inputs directly to the WKPND_B logic, without also having an input from WKEN_B. This indicates that WKPND_B can operate independently of WKEN_B until their outputs join at the AND gate to cause the actual interrupt.

Nearly every micro I've worked with operates in this fashion: each interrupt has both a pending bit and an enable bit, and the pending bit is set whether the enable bit is also set or not. The only (and very unfortunate) exception to this that I've ever seen is the lack of a pending bit for RTCC overflow in the SX20/28.

-Phil

Wayne G

Thanks Phil

Personally I can't remember a micro that I have worked with that had this feature which is why I was a little baffled. Would be nice if they mentioned it in the text (along with correcting some of the errors).

Wayne