Automatically Detecting Crystal Frequency
Phil Pilgrim (PhiPi)
Posts: 23,514
Okay, the title's a bit overstated, but here's been my problem: I've got two Propeller platforms that I work with regularly, one that uses a 5MHz crystal; the other, 10MHz. I've got programs that I use with both platforms, and I'm constantly forgetting to change the _CLKMODE constant to accommodate the platform I'm using. So I've come up with a way to detect which crystal the Prop is running on. That way I can leave the _CLKMODE and _XINFREQ set to one pair of values and forget about it.
The detection depends upon the fact that a counter's PLL must have a basis frequency between 4MHz and 8MHz to be stable. The upper end is, in fact, higher than that, and the free-running x1 frequency is closer to 15MHz — at least on the units I've checked. So, in theory, if the _CLKMODE is set to pll8x with a 5MHz crystal (clkfreq = 40MHz), and you set up a PLL counter to divide the clock by four (basis frequency = 10MHz), you should get a stable and predicatable PLL output. However, with a 10MHz crystal, the basis frequency doubles to 20MHz, and the PLL should fail to give a stable output.
Taking this into consideration, and not wanting to use any pins, I looked at Chip's RealRandom object for inspiration. He uses the PLL in a different way to generate random numbers, but the part I took advantage of was using WAITVID to determine the PLL output's actual frequency. If it's the value predicted from FRQA and VSCL, then it must be stable, the crystal must be 5MHz, and I can change the clock mode to pll16x. If not, then the crystal must be 10MHz, and I can leave the clock mode at pll8x.
Here's the sample code I used to test the object, which is attached below:
With both 5MHz and 10MHz crystals, the output frequency of pin A0 was the hoped-for 100Hz.
Now, I have no way of knowing yet how stable this code is, so use at your own risk. There are some, as yet, unanswered questions:
1. Is a PLL counter always stable and predictable with a basis frequency of 10MHz?
2. Is it always off at 20MHz?
3. Assuming it's stable, is the delay time using WAITVID always exactly the same amount? (This is a legitimate question, since the PLL is, after all, an analog circuit.)
I'd be interested in others' experience with this. I don't plan to post the object in the OBEX just yet.
-Phil
Post Edited (Phil Pilgrim (PhiPi)) : 5/23/2009 7:53:00 PM GMT
The detection depends upon the fact that a counter's PLL must have a basis frequency between 4MHz and 8MHz to be stable. The upper end is, in fact, higher than that, and the free-running x1 frequency is closer to 15MHz — at least on the units I've checked. So, in theory, if the _CLKMODE is set to pll8x with a 5MHz crystal (clkfreq = 40MHz), and you set up a PLL counter to divide the clock by four (basis frequency = 10MHz), you should get a stable and predicatable PLL output. However, with a 10MHz crystal, the basis frequency doubles to 20MHz, and the PLL should fail to give a stable output.
Taking this into consideration, and not wanting to use any pins, I looked at Chip's RealRandom object for inspiration. He uses the PLL in a different way to generate random numbers, but the part I took advantage of was using WAITVID to determine the PLL output's actual frequency. If it's the value predicted from FRQA and VSCL, then it must be stable, the crystal must be 5MHz, and I can change the clock mode to pll16x. If not, then the crystal must be 10MHz, and I can leave the clock mode at pll8x.
Here's the sample code I used to test the object, which is attached below:
[b]CON[/b]
[b]_clkmode[/b] = [b]xtal1[/b] + [b]pll8x[/b]
[b]_xinfreq[/b] = 10_000_000
[b]OBJ[/b]
clk : "[b]clkset[/b]"
[b]PUB[/b] Start | time
clk.set
[b]dira[/b][noparse][[/noparse]*0]~~
time := [b]cnt[/b]
[b]repeat[/b]
[b]waitcnt[/b](time += clkfreq / 200)
[b]outa[/b][noparse][[/noparse]*0]~~
[b]waitcnt[/b](time += clkfreq / 200)
[b]outa[/b][noparse][[/noparse]*0]~
With both 5MHz and 10MHz crystals, the output frequency of pin A0 was the hoped-for 100Hz.
Now, I have no way of knowing yet how stable this code is, so use at your own risk. There are some, as yet, unanswered questions:
1. Is a PLL counter always stable and predictable with a basis frequency of 10MHz?
2. Is it always off at 20MHz?
3. Assuming it's stable, is the delay time using WAITVID always exactly the same amount? (This is a legitimate question, since the PLL is, after all, an analog circuit.)
I'd be interested in others' experience with this. I don't plan to post the object in the OBEX just yet.
-Phil
Post Edited (Phil Pilgrim (PhiPi)) : 5/23/2009 7:53:00 PM GMT
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
-Phil