CPLD's and the Propeller
Hanno
Posts: 1,130
I'm much more of a software geek than hardware or the in-between fpga/cpld. However, with the recent thread on bursting to/from external memory, we seem to have hit on a new and powerful way of interfacing to the Propeller- now, I need to learn something new! Can someone enlighten me and others how to work with those devices? What hardware do we need? What software tools are available to program the device? What are some possible applications of cpld and the propeller?
Hanno
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Download a free trial of ViewPort- the premier visual debugger for the Propeller
Includes full debugger, simulated instruments, fuzzy logic, and OpenCV for computer vision. Now a Parallax Product!
Hanno
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Download a free trial of ViewPort- the premier visual debugger for the Propeller
Includes full debugger, simulated instruments, fuzzy logic, and OpenCV for computer vision. Now a Parallax Product!
Comments
You could create an FPGA Propeller with 64 I/O pins and/or a separate HUB memory [noparse]:)[/noparse]
Don't know how Parallax would feel about that, but the FPGA cost would be over to 6x the Propeller.
I'm working on a Propeller simulation behavioural model for testing with other CPLDs; this is very
different from a "runnable" image and not at all intended to be used in real hardware.
One needs a board with an FPGA or CPLD. CPLDs can be cheap but small.
FPGA's are more expensive and require external memory or connection to CPU to download an image.
Prototyping kits are available from Digikey, etc... But none have a Propeller.
One needs to learn Verilog, AHDL, or VHDL. Verilog is less software-ish.
Of course a compiler/synthesizer is important. I'm also using a separate program for simulation.
Most software is free ... except for the CPLD on the HX512 (maybe I'm wrong ... someone correct me?).
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
The FPGA function is defined in a Verilog (or VHDL) program. Look at the attachment, you could write this kind of code (part of the CPU Verilog code).·FPGA suppliers deliver translators·like Altera Quartus, that·translate Verilog·code into bitpatterns that control·the·interconnections on the FPGA. Low end devices have on board flash memory, high end devices are RAM based.·RAM is·loaded·using the JTAG interface during development/debug, or·from·an external EEPROM·much like the propeller does.
Nico Hattink
John Abshier
Cool [noparse]:)[/noparse] [noparse]:)[/noparse] [noparse]:)[/noparse] I don't remember seeing this before today. Hope you don't mind a PM for more detail.
I'll finish what I started, but a completed cycle-accurate design for simulation would be speed other things along.
Thanks for the link John.
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
I only worked with the XILINX XC9572 so far. What you need for a start is very inexpensive. Just two 74125 and some resistors and capacitors and a parallel interface. XILINX offers the software for free (you only need to register), it's called ISE WebPack. What you need to learn is a Hardware Description Language. In my first try I used ABEL (I think long form is "Abstract Boolean Equation Language) - but lately I read that this is an old language and very rarely used nowadays. But I liked it and it seems to be the "Assembler" of CPLD development.
Nowadays the most common language is Verilog and is the "C" of CPLD development, so to say. But that I have to learn as well.
As far as I know Altera also gives the software for free and I could bet that Lattice is doing so as well.
How to work with it ... well ... you can start without hardware first. Learn whatever language you prefer. What the CPLD gives you is a lot of configurable flipflops called macrocells and a big matrix of AND and OR terms. This matrix is fed with the input-pins, the flipflop outputs, with result of other terms, clock and reset signals ....
What you do when you program the CPLD is telling the Matrix which inputs to use for a term and what flipflop to route it to. The XILINX tool includes a simulator. You define the input vector and what your expected output would be and the tool then checks if the CPLD would behave like expected.
FPGA is next on my list of things to try out/learn. But for the memory thread an FPGA would be oversized.
Ah ... there is an application note from XILINX how to reprogram the CPLD via microcontroller. That would give a nice Propeller/CPLD development environment.
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My new unsecure propmod both 1x1 and full size arriving soon.
Altera Quartus lets you do that.
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
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My new unsecure propmod both 1x1 and full size arriving soon.
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--Steve
Propalyzer: Propeller PC Logic Analyzer
http://forums.parallax.com/showthread.php?p=788230
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My new unsecure propmod both 1x1 and full size arriving soon.
This may be more than what your looking for but I did notice it on elektor.com
Starter Kit CPLD (EB287)
This CPLD development solution, based on E-blocks, contains everything you need to investigate advanced digital electronics using CPLD technology.
www.elektor.com/products/e-blocks/starter-kits/starter-kit-cpld.530386.lynkx
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Aka: CosmicBob
maybe someone here already has a dev kit and I can send a logic diagram and buy the programed chips off them.
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My new unsecure propmod both 1x1 and full size arriving soon.
www.geocities.com/leon_heller/pld_starter.html
I use Altera MAX II CPLDs these days; they are actually small FPGAs, internally.
Leon
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Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
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My new unsecure propmod both 1x1 and full size arriving soon.
Leon
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Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle