new propeller ?

Olli

Hi everybody,

what about adding some extra registers to the new Propeller chip.
Maybe some pos and neg edge detecting. Could keep coding a bit smaller.

"esra, esrb ( edge status register A or B )" tells me a rising or falling edge has been detected on pin , reading tells me a edge has been detected or not , writing a 1 to it clears flag

"ecra, ecrb ( edge config register A or B )" decides pos edge or neg edge detection

or adding some hardwired I2c, serial, SPI registers on chip. ( sure that can(is) be done by a cog in software..... )

or some ADC functions like in Atmega.
or some DAC functions

okay price of that would rise.... but good hardware ....good price

and another maybe silly question. Why operating voltage was set to 3.3V and not 5V.

stevenmess2004

Olli said...
Maybe some pos and neg edge detecting. Could keep coding a bit smaller.

"esra, esrb ( edge status register A or B )" tells me a rising or falling edge has been detected on pin , reading tells me a edge has been detected or not , writing a 1 to it clears flag

"ecra, ecrb ( edge config register A or B )" decides pos edge or neg edge detection

Have a look at the waitpeq and waitpne. You can use these to find rising and falling edges. You can also setup the counters to count rising or falling edges.

said...
or adding some hardwired I2c, serial, SPI registers on chip. ( sure that can(is) be done by a cog in software..... )

There objects in the object exchange for most of these and with a little bit of code you can get the timers to output a serial bitstream.

said...
or some ADC functions like in Atmega.

With a couple of resistors and capacitors you can make a sigma-delta ADC. The demo board has one on the mic input

said...
or some DAC functions

You can generate PWM signals with the timers which you just need to put through a low pass filter to get a DAC. The demo board has two connected to the headphone jack.

said...
okay price of that would rise.... but good hardware ....good price [noparse][[/noparse]/qote]
Yep, good reason not to do it. The propeller is priced at the high end of market already. Also, the idea of the propeller was to get rid of things that were often not used.

said...
and another maybe silly question. Why operating voltage was set to 3.3V and not 5V.

I think mainly because the process they used to manufacture the chip couldn't take 5V. It also helps to reduce power consumption.

Olli

counters can do edge detection, but there are only 2 per cog. And waitpeq and waitpne causes the cog to stop until.... but stopping is a waste of power. Also waitcnt is often a waste of power.

And with some edge detecting registers ( I think not quite hard to add at chip ) there are some nice possibilities. not only for edge detection, if implemented clever

Combine "esra,ecra" with Dira and u might get some extra functions.

setting an output pin high for one clock cycle etc...

Cluso99

Yes. The process and switching speed required 3V3 which is a standard. The new PropII will be 1V8 once again due to the process and speed. Chip's webinar explains this better.

If you look at some of the leading FPGA's they are using 1V2, 1V and 0V9. So now extra silicon (and pins) has to be devoted to various I/O external voltages. Chip also explained that as a consequence of the lower voltage and higher switching speed there is also more leakage and so current consumption goes up.

Thats progress for you

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stevenmess2004

Olli said...
counters can do edge detection, but there are only 2 per cog. And waitpeq and waitpne causes the cog to stop until.... but stopping is a waste of power. Also waitcnt is often a waste of power.

Check the data sheet. Whenever a cog is in one of the wait instructions it uses almost no power.

However, the real problem is the time, cost and compatibility problems involved in making changes to the chip. It would probably take several months of an IC layout engineers time, new stencils may have to be manufactured and the chip will be physically larger which would all make a pretty significant difference in price. Then the changes could easily break a lot of existing code, the spin interpreter would need rewriting and all the documentation would need to change.

The changes you have suggested could be useful in some situations. However, before anything is included in a chip it must first be judged whether it is more important than some other feature. In this case, most of the changes you have asked for are reasonably well covered by functions of the chip and therefore don't have a high priority.

Olli

quote steve: "Check the data sheet. Whenever a cog is in one of the wait instructions it uses almost no power."

With "waste of power" I meant waste of clock ticks not power consumption !

and maybe someone finds thats idea with edge detection registers useful...

hairymnstr

An idea that struck me earlier when I looked at this was that it might be handy if there were some additional shared cog registers, like ina outa, I've seen some tricks for inter-cog communications using pins. How about if there were one or two "virtual" IO registers a port C and D for example, but with no IO attached.

Maybe this would be too expensive in terms of silicon or more likely cog memory addresses, maybe it would not be useful (had I heard that the prop II is meant to have faster hub access somehow).

Something to think about.