I2C reset (part of protocol or by device/manufacturer only?)

Zoot

I have had a only a bare handful of projects where under certain circumstances an I2C slave may "lockup" (generally by not releasing SCL if a lockup happens during clock stretching -- masters that do not timeout under these circumstances usually fall into their own endless loop as well because SCL never goes high). There are workarounds of course: polling SCL, bit-banging I2C routines to ensure that I2C transactions timeout while waiting for a slave to release a line, power cycling the slave, etc.

However, I came across this tidbit in a datasheet from Atmel (an I2C 32kbit SOIC EEPROM) and was wondering if this is part of the I2C protocol proper, or just a (widely-used?) convention followed by some manufacturers but not necessarily all.

doc said...
After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.

Anybody know about this?

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InSilico

According to the I2C spec:

I2C-bus compatible devices must reset their bus logic
on receipt of a START or repeated START condition
such that they all anticipate the sending of a slave
address, even if these START conditions are not
positioned according to the proper format.

So·a·START condition is basically the same thing as a reset. I don't see anywhere in the spec that says 9 clock cycles need to precede that. Maybe it's a workaround for some I2C devices with bugs in the silicon that prevents a proper reset after receipt of a START condition.

Bean

The 9 clocks are needed in case the other device is sending a zero byte (hence holding SDA low for eight clocks).
You don't HAVE to send all 9 clocks, after each clock you are just looking for SDA to go high.
If SDA doesn't go high after 9 clocks, then something is really screwed up.

Bean.

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Zoot

Thanks.

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OwenS

If SDA is low for 9 clocks, thats where SMBus comes in: The hardware in SMBus devices must reset if SDA is held low for a certain amount of clocks IIRC