Questions To Chip on Prop 2?

Sapieha

Hi Chip.

I have questions on Prop2 functions You implements:

1. Many TFT VGA Displays wil have Clock pulse on every pixel.

? Is it posible to You implement this.

2. In Prop1 You have only fast IO output mode.

? It is posible to have TriState mode with RD/WR signals from Prop2

. Model:

. After DIRx Port is in TRiState.

. If I read (8 else 16 bit wide) from it .. It simply read Port with siglanling on one RD pin

. if I Write to Port (8 else 16 bit wide) It output to Port and signaling on WR pin

. To that it must be posible to dedicate (8 else 16 bit wide) Port As Tristate and 2 Pins as RD/WR



Ps. Have more questions

But them can wait

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Nothing is impossible, there are only different degrees of difficulty.
For every stupid question there is at least one intelligent answer.
Don't guess - ask instead.
If you don't ask you won't know.
If your gonna construct something, make it·as simple as·possible yet as versatile as posible.


Sapieha

Post Edited (Sapieha) : 4/18/2009 5:23:18 AM GMT

cgracey

Sapieha said...

Hi Chip.

I have questions on Prop2 functions You implements:

1. Many TFT VGA Displays wil have Clock pulse on every pixel.

? Is it posible to You implement this.

This is possible. What is the relationship between the clock signal and data bits, though (setup times, clock polarity, etc.)?

2. In Prop1 You have only fast IO output mode.

? It is posible to have TriState mode with RD/WR signals from Prop2

. Model:

. After DIRx Port is in TRiState.

. If I read (8 else 16 bit wide) from it .. It simply read Port with siglanling on one RD pin

. if I Write to Port (8 else 16 bit wide) It output to Port and signaling on WR pin

. To that it must be posible to dedicate (8 else 16 bit wide) Port As Tristate and 2 Pins as RD/WR

·These things are possible, but could you elaborate on what other signals would be needed to complete this scheme (like a clock signal)?

Ps. Have more questions

But them can wait

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Chip Gracey
Parallax, Inc.

Sapieha

Hi Chip.

Yes I can elaborate on both poroblems.

Tomorrow I wil post Timing on it.

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Nothing is impossible, there are only different degrees of difficulty.
For every stupid question there is at least one intelligent answer.
Don't guess - ask instead.
If you don't ask you won't know.
If your gonna construct something, make it·as simple as·possible yet as versatile as posible.


Sapieha

Sapieha

Hi Chip.

Pictures HX8218-A.jpg and LTA070B0N0A.jpg is timings on TFT LCDs on RGB Clock

Tristate IO timings is for easy implementing SRAM/IO BUS structures with not ned to switch DIRx for every Read/Write cycle

It is (8 else 16 bit wide) BUS and 2 RD/WR pins.
For flexiblity it is desired to have posiblity to direct RD/RW to any PIN pair on Prop2 in and of 32 Pins group

·

·

Ps. Clock frequencies on TFT RGB DOTs is same as DOT frequencies on VGA Displays

Ps 2.· I forgot to say that RD/WR signals must have posiblites to have programable Wait states

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
For every stupid question there is at least one intelligent answer.
Don't guess - ask instead.
If you don't ask you won't know.
If your gonna construct something, make it·as simple as·possible yet as versatile as posible.


Sapieha

Post Edited (Sapieha) : 4/18/2009 8:03:52 AM GMT

Microcontrolled

I don't mean to intrude on your post but I have wondered if the prop 2 is going to be able to use an SD card or other mass storage device as
program storage. I saw the webinar video and it sounded like this was what you where saying. It would be a HUGE feature that I would be
looking forward to.

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Toys are microcontroled.
Robots are microcontroled.
I am microcontrolled.

Bill Henning

SD is 1/4 bits wide and far too slow to "run" code in; it is only useful for file storage.

microcontrolled said...
I don't mean to intrude on your post but I have wondered if the prop 2 is going to be able to use an SD card or other mass storage device as
program storage. I saw the webinar video and it sounded like this was what you where saying. It would be a HUGE feature that I would be
looking forward to.

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www.mikronauts.com - a new blog about microcontrollers

Bill Henning

Exposing the pixel clock, ideally active only during "visible" pixels, would allow feeding TFT and older STN etc panels easily from a Prop.

Exposing the "LATCH INPUT" as a "~RD" and "LATCH OUTPUT" as "~WR" would allow for fast interfacing to memory, as well as D/A converters etc.

Both would be very good things [noparse]:)[/noparse]

Chip Gracey (Parallax) said...

Sapieha said...

</P>
2. In Prop1 You have only fast IO output mode.

? It is posible to have TriState mode with RD/WR signals from Prop2

. Model:

. After DIRx Port is in TRiState.

. If I read (8 else 16 bit wide) from it .. It simply read Port with siglanling on one RD pin

. if I Write to Port (8 else 16 bit wide) It output to Port and signaling on WR pin

. To that it must be posible to dedicate (8 else 16 bit wide) Port As Tristate and 2 Pins as RD/WR



Ps. Have more questions

But them can wait
</FONT>

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www.mikronauts.com - a new blog about microcontrollers

kwinn

Sapieha, great idea. Looking at the timing and signals I wonder if it would be possible to combine the video/ram/I/O into a single subsystem. The output to the TFT looks very similar to the I/O and memory write timings. The read timings are also similar, the major difference being the data direction and having the data available earlier.

Ale

Sapieha: The ahem, xmos chip, can do most of what you want. Its port hardware is quite versatile (I wish the prop had something like that!). Sadly it only comes in BGA unfriendly packages :-(


Edit: I do not know about the timing but if they keep adding stuff (because we ask for it!) it will be taped-out in 2020 We need (want want want) it now