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Generating high frequency clock pulses — Parallax Forums

Generating high frequency clock pulses

RileyRiley Posts: 1
edited 2009-03-31 07:19 in Propeller 1
I'm a little new to the propeller and its features, and have a question about generating high frequency clock pulses with the propeller chip. Would it be possible to generate stable clock pulses to drive another chip in the range of 10-20 MHz? Could this be done using CTRA/B? I read something about using these counters to do this, but I found the documentation to be a little lacking in describing what the different timer modes are for.

Thanks,
Riley

Comments

  • Mike GreenMike Green Posts: 23,101
    edited 2009-03-30 22:55
    See:·http://www.parallax.com/tabid/442/Default.aspx

    Download the application note (AN001) on the counters.· If you have a proper power of two submultiple of the system clock, you can get an output as stable as the system clock itself.· If it's not a power of two submultiple, you'll get some jitter.· The counters can use a PLL to multiply the system clock to frequencies up to about 160MHz which can then be divided down.
  • virtuPICvirtuPIC Posts: 193
    edited 2009-03-31 06:44
    Be aware that the prop gets its clock from some single fixed source. Typically some quartz crystal. It has a PLL inside, but this cannot be programmed freely. For instance, if you are running your prop with a 5 MHz crystal and a PLL factor of 16 you'll get 80 MHz reference clock and using the internal counters you can get all integer divisors of this frequency. (Sorry, don't know how to formulate this best.) In the are of 10 MHz to 20 MHz these are 80/8, 80/7, 80/6, 80/5, 80/4 MHz.

    Not very fine grained. If you just need some clock pulses 'in the area of 10...20 MHz it's okay. If you want to tune, e.g. to a radio transmitter you'll need some extra hardware. TI has PLL chips that can be programmed via serial connection to a prop or any other controller.

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  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    edited 2009-03-31 07:19
    Actually, the available counter PLL output frequencies are given by:

    ····f0 = CLKFREQ * n / 232, where 1 < n < 231 such that 4 MHz < f0< 8MHz, and
    ····fout = f0/16, f0/8, f0/4, f0/2, f0, f0*2, f0*4, f0*8, or f0*16

    The amount of jitter is roughly inversely proportional to the number of consecutive least-signficant zeroes in the binary expansion of n.

    -Phil

    Post Edited (Phil Pilgrim (PhiPi)) : 3/31/2009 7:30:00 AM GMT
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