SHIFTIN mode PRE / POST and I2C protocol do not match
vaclav_sal
Posts: 451
Making SHIFTIN work with a particular device is a matter of matching the mode and number of bits to that device's protocol. Most manufacturers use a timing diagram to illustrate the relationship of clock and data. Items to look for include: 1) which bit of the data arrives first; most significant bit (MSB) or least significant bit (LSB) and 2) is the first data bit ready before the first clock pulse (PRE) or after the first clock pulse (POST). The table below shows the values and symbols available for the Mode argument.
Parallax folks, please help me to "translate·" this description to I2C protocol.
Figure 1-2 on attached document shows "serial·input timing" where the MSB data is valid DURING the clock pulse.
The SHIFTIN PRE or POST modes clearly indicates that data will be read· BEFORE (1st) clock pulse or before 2nd clock pulse. It appears to miss the time when I2C protocol states that the data is valid - during the clock pulse!
I am experimenting with 23k256 chip and can read / write to the status·register. The write / read to memory itself is giving me pretty random and unpredictable results so far.
I can post the code for illustration·later , but I need this·SHIFTIN mode description clarified first.
Thanks in advance.
Cheers
Any spelling errors are due to missing electrons.
Parallax folks, please help me to "translate·" this description to I2C protocol.
Figure 1-2 on attached document shows "serial·input timing" where the MSB data is valid DURING the clock pulse.
The SHIFTIN PRE or POST modes clearly indicates that data will be read· BEFORE (1st) clock pulse or before 2nd clock pulse. It appears to miss the time when I2C protocol states that the data is valid - during the clock pulse!
I am experimenting with 23k256 chip and can read / write to the status·register. The write / read to memory itself is giving me pretty random and unpredictable results so far.
I can post the code for illustration·later , but I need this·SHIFTIN mode description clarified first.
Thanks in advance.
Cheers
Any spelling errors are due to missing electrons.
pdf
336K
Comments
From the perspective of the EEPROM, "serial input timing" would correlate to a SHIFTOUT command from the Stamp... likewise "serial output timing" would correlate to a SHIFTIN command from the Stamp.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Beau Schwabe
IC Layout Engineer
Parallax, Inc.
(www.parallax.com/Portals/0/Downloads/docs/cols/nv/vol3/col/nv85.pdf).
This SHIFTIN mode description "does not compute". It seems to work with POST mode. But I think my status·register mode is wrong also.
Thanks
For Pre shift modes, the data is sampled before the first clock pulse.
For Post shift modes, the data is sampled before the second clock pulse.
Another way to look at it...
For Pre shift modes, the data is sampled before the clock pulse.
For Post shift modes, the data is sampled after the clock pulse.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Beau Schwabe
IC Layout Engineer
Parallax, Inc.
Post Edited (Beau Schwabe (Parallax)) : 3/26/2009 8:53:14 PM GMT
The 23K256 does not use the I2C interface but does use SPI (Serial Peripheral Interface).
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
························ Craig Eid
··········· Triad Research and Development
Electical Engineering Design and Consulting Services
··················· www.TriadRD.com
So “the translation is”· - the SHIFTIN description is using misleading·terminology.
The PRO samples the data on leading edge of the clock pulse and the POST does same on trailing edge of the same pulse.
The description and the associated picture lead me to believe they are talking about two different pulses. Silly me.
I just used I2C to demonstrate the issue.
Thanks guys for you contributions, my code now working just fine.
No more missing electrons.
BTW the interpreter does not·flag it as error when I erroneously used MSBFIRST mode in SHIFTIN.
·Cheers