FSR Register, BANK Instruction and Resister Bank

stephenwagner

I am having issues understanding the FSR and register bnak addressing.

The below program, Which is similar to Gunther Daubach Prog. the SX TUT010.SRC, regardless of the FSR.4 bit selection, the program runs the same. What am I missing here? I think I understand the lower 4 bits and the upper 3 bits, but not FSR bit No. 4. According to the SX data sheet. 1=Bank Enable, 0=Bank Disable. Whether I comment out "Setb· fsr.4" or not, the program runs the same.

; TUT011.SRC
;
;

---

; Sample tutorial code published in
; "Programming the SX Microcontroller" 2nd Edition by Guenther Daubach
; Copyright (c), by Parallax Inc. 2004
;

---

FSRWATCH equ $04
include "Setup28.inc"
RESET······ Main
org········ $11················ ;· 1
BankA······ equ $············· ;· 2
counter1 ds 1·············· ;· 3
org········ $33················ ;· 4
BankB······ equ $·············· ;· 5
Counter2··· ds· 1·············· ;· 6
···············································
org········ $55················ ;· 7
BankC······ equ $·············· ;· 8
Counter3··· ds· 1·············· ;· 9
org········ $7c················ ; 10
BankD······ equ $·············· ; 11
Counter4··· ds· 1·············· ; 12
WATCH FSRwatch, 8, UBIN
org········ $100··············· ; 13
Main
; Includes code to clear all data memory
;
;include "Clr2x.inc"
···············································
; Testing data memory addressing
TestAddr
Setb· fsr.4

· bank····· BankA·············· ; 21
· inc······ Counter1··········· ; 22
· bank····· BankB·············· ; 23
· inc······ Counter2··········· ; 24
· bank····· BankC·············· ; 25
· inc······ Counter3··········· ; 26
· bank····· BankD·············· ; 27
· inc······ Counter4··········· ; 28
· jmp······ TestAddr··········· ; 29

SJW

Bean

Only bits 5-7 of FSR are used to set the bank. FSR.4 doesn't have any affect on it.

FSR bits 4-7 only are used when you use IND to do indirect addressing.

On the SX28 if FSR.4 is clear, you will acess global memory $00 to $0F with IND according to FSR.0-3 bit values (it doesn't matter what FSR.5-7 are, you will still access global memory).

I hope this makes it a little clearer.

Bean.

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There is a fine line between arrogance and confidence. Make sure you don't cross it...

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stephenwagner

Bean,

Thanks.

What registers can I·WATCH to see this effect.

I am also having issues with direct and indirec addressing.



SJW

Bean

In the debugger just look at the "Registers" window. There will be a blue box around whatever memory address FSR is pointing to.

What issues are you having with direct addressing ?

Bean.

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There is a fine line between arrogance and confidence. Make sure you don't cross it...

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stephenwagner

Bean,

Thanks for your support.

Let me digest some of what you stated, poke around with some examples, and figure this out.

I will eventually figure it out. There is a reason.



SJW