What kind of flip-flop do I need for this ?

Bean

I have two digital inputs A and B, and one digital output.

I would like the output to go high on the rising edge of INPUT-A.
And then go low again on the next rising edge of INPUT-B.

The output needs to stay low until the next rising edge of INPUT-A even though INPUT-B is pulsing.

I thought I needed a Set-Reset flip-flop, but that doesn't seem to do it.

Help....I'm not that good with discreet logic.

Bean.



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·The next time you need a hero don't look up in the sky...Look in the mirror.


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Philldapill

Bean, you could probably use two set-reset flip flops. The first, would be the setup you described, then the second would cascade from the first. You might need a NAND gate in there, too... I'll think about it some more.

PJAllen

How about a 74_123 or 74_221 and use 'B' on /CLR?

Post Edit -- pic added.· _123's A_pin to GND.

Post Edited (PJ Allen) : 1/20/2009 2:29:06 AM GMT

Bean

Either edge can be rising or falling it doesn't matter. Also the INPUT-A will not change during the output high time. I don't know if that makes it any easier.

This is for a timing application, so the least amount of jitter is needed.

INPUT-A is a 152 Hz square wave, INPUT-B is a 39KHz·square wave. I need to get a pulse width that represents the phase error between the two.

Bean.

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·The next time you need a hero don't look up in the sky...Look in the mirror.




Post Edited (Bean (Hitt Consulting)) : 1/20/2009 1:09:58 AM GMT

Phil Pilgrim (PhiPi)

Terry,

Try this:



An incoming edge on A will set the top FF. An incoming edge on B will clear A and preset B. You may need an RC filter on the input of B's preset to make sure A's clear gets a long enough pulse. Also, there's no predicting how this circuit will power up. If that matters, a strategically-connected supervisor chip would help.

-Phil

Addendum: BTW, is this a "forward-only" pulser for a quadrature encoder? If it is, there's an even better way to hookup the 'HC74s.

Post Edited (Phil Pilgrim (PhiPi)) : 1/19/2009 11:52:24 PM GMT

Bean

Phil,
Thanks. I will have an SX in this design. I tried using the SX to do the timing, but I can't get enough resolution. So I wanted to use an analog solution.
The output will go to an RC circuit and I'll use an ADC to measure the voltage.

Bean.

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·The next time you need a hero don't look up in the sky...Look in the mirror.


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Beau Schwabe

Bean,

Did you ever try Phil's solution? Did it work?

Just as a mind exercises I put something together with "glue-logic" based on your requirements. Not that it's a better solution, I think the 74HC74 is an elegant solution if it works.

I wonder what kind of results you could get if you divide down the 39kHz by a factor of 256 with a simple binary counter and use an AD630 configured as a Phase detector.... then you could determine lead and lag phase differences.

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Beau Schwabe

IC Layout Engineer
Parallax, Inc.

Carl Hayes

Here's how I would do it.· See the attached image.· A negative edge on A sets Q high, and a negative edge on B sets Q low.

Your original intuition was correct -- all you need is an R-S flipflop, but you also need the capacitors and resistors to change your edges into pulses.

The two NAND gates (perhaps 74LS00) are interconnected to form an R-S flipflop.· Of course any flipflop that has set and reset inputs could be used as well.· If the set and reset require positive pulses instead of negative ones (for instance, if you use NOR gates instead of NAND gates and the resistors go to ground instead of to positive), the flipflop will change state at the positive-going edges instead of at the negative-going edges.

About 0.01 μF and 10KΩ ought to work.




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· -- Carl, nn5i@arrl.net

Post Edited (Carl Hayes) : 1/21/2009 5:51:21 PM GMT