VSS and VDD pins

s2jesse

Im having fun messing around designing some boards for the first time and my question is...
Is it neccisary / a good idea·to supply vdd and vss to all of the vss and vdd pins on the prop or can i leave some unconnected and should you always place a .1uf cap between each? is it also pretty much rule of thumb to do it on any ic? such as mcp3208?


thanks
Jesse

Jay Kickliter

I think most people agree that you should have a 1 or .1 uF capacitor on any VDD pins, even for your EEPROM and ADC. Even bigger on something that occasionally draws a bit of current, like an SD card. I can't tell you whether or not it will work correctly with only 1 pin hooked up. Even if it did, you might run into problems when running at higher speeds, due to higher current draw and voltage drop.

Mike Green

You must supply Vdd and Vss to all of the pins provided. One Prop chip failure mode (system clock PLL failure) has been partially attributed to leaving one or more of these unconnected.

You do need to connect at least one 0.1uF cap between Vdd and Vss of each chip, particularly for complex chips like a processor or ADC. PCB board traces have some inductance and that will prevent power from getting to the chip from the source on the PCB for a short period of time. The 0.1uF caps provide a power reservoir for a short time. Sometimes you can get away with using one 0.1uF cap for each pair of ICs when they're physically adjacent on the board and the power traces are short.

s2jesse

alrighty thanks guys!

Leon

You also need wide tracks for your supply and ground connections.

Leon

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Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle

Jay Kickliter

Leon, how wide do you use? I've been using 40 mil, because I have the room. I image that is a bit excessive. I've also been using huge traces for the clock, I hear the Propeller is sensitive about that.

Phil Pilgrim (PhiPi)

I use 20- to 50-mil power traces to the Prop, depending on how long they are. All Vss pins get routed using adjacent vias to the groundplane on the bottom of the board. I also include a powerplane for Vdd underneath the chip on the top side. Sometimes I need to route signals through it, so it can get broken up, requiring connecting traces on the grondplane side. I typically use two 1uF ceramic bypass caps on opposite sides of a QFP. If my designs had room for four, I'd use four 0.47uF caps instead. But that opportunity has never come up. It's best to treat bypass caps on a PCB like peanut butter on toast: a thin, evenly-distributed layer is better than a few thick dollops.

BTW, a groundplane should not be treated as some magic monolithic trace. This is particularly true when it gets broken up a little by those few short signal traces that need to be routed there. You have to pay attention to the ground current flows. I call it the "feng shui" of PCB design. I will even add deliberate breaks to the groundplane from time to time, in order to coerce the return flow along a certain route, for example, between the power connector at the edge of the board and the voltage regulator.

As to the clock traces, I've only ever used 8-mil traces there and haven't encountered any problems. The main thing is to keep them short. Too wide a trace might result in too much capacitance with the ground plane.

-Phil

Leon

I use 25 or 50 mil tracks for power and ground, generally, depending on how much room I have. I often use copper pour for the ground connections.

I use ordinary signal tracks for crystals, to avoid introducing additional capacitance, as Phil has pointed out.

Leon

▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle

s2jesse

good info...

Just to keep the convo flowing a little... here's my first attempt at a board.. It was made for a little project i was making to control· a camera for astronomy. I aslo added some other features such as the ability to trigger·shutter based on other external sensors. Lcd goes on top of the prop.



I etched it myself as test all seemed to work and i sent it off to· pcb house(batchpcb) just for fun and to learn how it comes back[noparse]:)[/noparse] As you can see those red traces were more of a test to see how the top layer comes back etc. I didnt want to mess with a top layer when etching myself but wanted to see how the vias etc worked.

So now·I know my board is missing the .1uf caps [noparse]:)[/noparse] and besides more use of the second layer what else can be improved upon?

Post Edited (s2jesse) : 1/11/2009 12:57:32 AM GMT