Timing of writing PHSx
Andrew E Mileski
Posts: 77
Sorry if this is noted elsewhere, but I couldn't find anything via Google using site:forums.parallax.com
I'm trying to output 2 cycle long bit periods back-to-back using multiple counters on multiple synchronized cogs.
As I understand it, writes to PHSx in instructions as dest actually write to shadow memory first which is then latched into the counter.
Q1: If a counter is running, does the first potential accumulate after writing PHSx happen on clock cycle M + 5 (stage 5) or M + 6 (the next stage 1)?
Q2: In NCO / PWM modes, can PINA change immediately upon writing of PHSx[noparse][[/noparse]31] on clock cycle M + 5, or does an accumulate need to happen first?
Thanks.
I'm trying to output 2 cycle long bit periods back-to-back using multiple counters on multiple synchronized cogs.
As I understand it, writes to PHSx in instructions as dest actually write to shadow memory first which is then latched into the counter.
Q1: If a counter is running, does the first potential accumulate after writing PHSx happen on clock cycle M + 5 (stage 5) or M + 6 (the next stage 1)?
Q2: In NCO / PWM modes, can PINA change immediately upon writing of PHSx[noparse][[/noparse]31] on clock cycle M + 5, or does an accumulate need to happen first?
Thanks.
Comments
It looks like PHSA and any resulting pin changes are both written "almost immediately" during the R cycle. Here's a program I wrote to test this:
Here's the resulting scope trace:
The delay from writing the first pin directly to writing the second one indirectly via PHSA is 52 ns, or 2 ns (a fraction of a cycle) longer than one instruction time. I repeated the experiment by just writing both pins directly in the same sequence. The delay was 50 ns. So the extra 2 ns definitely comes from writing PHSA and the result percolating to the pin.
-Phil
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