Prop Timing diagram?

Rayman

I'm looking for the exact timing for the Props Input pins with regard to the clock...

Thought this would be in the datasheet, but I don't see it.
I don't even see any mention of whether the input is sampled on the rising edge or falling edge...

Nothing about a required hold time either...

Paul Baker

INA is sampled during the S stage, and IIRC it is latched at the end of the cycle. There are no setup or hold times other than the signal must be stable at the point it's latched.

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Paul Baker
Propeller Applications Engineer

Parallax, Inc.

Rayman

What are "S stage" and IIRC?
And, how do they relate to the rising edge of the clock?

Paul Baker

S is the source stage of the SDIR pipeline, the datasheet describes this, IIRC = if I recall correctly. Maybe I'm missing something, but how does the polarity of the clock matter since it is completely hidden from the user? For example, what is the polarity of the system (ie on which edge does the pipline progress), is it on the rising or falling edge? And does the answer have any practical meaning?

Perhaps if you provide a little more background on your question, I can understand why the polarity is important. The IIRC statement of my previous post is that I think the latch is in phase with the pipeline.

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Paul Baker
Propeller Applications Engineer

Parallax, Inc.

Post Edited (Paul Baker (Parallax)) : 11/11/2008 7:35:36 PM GMT

Rayman

I want to drive an ADC with the same clock as the Prop... I want to make sure the Prop is going to sample during the time of valid output from the ADC.

Paul Baker

Ah gotcha, I'll have to check. I'll get back to you when I have an answer.

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Paul Baker
Propeller Applications Engineer

Parallax, Inc.

Paul Baker

The answer is rising edge.

Here is the code I used to determine the answer,

'slave code
CON
  _clkmode = xtal1
  _xinfreq = 5_000_000
PUB go
  cognew(@run,0)
  repeat
DAT
        org 0
run     mov dira, #2
loop    mov tmp,ina
        shl tmp, #1 
        mov outa, tmp
        jmp #loop
tmp LONG 0

'master code
CON
  _clkmode = xtal1 + pll16x
  _xinfreq = 5_000_000
 
PUB go
  cognew(@run,0)
  repeat
 
DAT
        org 0
run     mov dira, #3
        mov frqa, freqa
        mov ctra, ctrav       wz                'z flag now set
        'pin 0 now oscillating at 5MHz
        mov tcnt, cnt
        add tcnt, offset
        waitcnt tcnt, #0
loop    muxnz outa, #2
        muxz outa, #2
        nop
        jmp #loop
 
ctrav  LONG %00100_000 << 23 + 0
freqa  LONG $1000_0000          '5MHz
offset LONG 13
tcnt   LONG 0
 

The slave simply copies whatever it sees on pin 0 to pin 1 (which is connected to an LED). The master starts a counter running P0 at 5MHz·which is connected to Xin of the slave, then it toggles P1 in a 5MHz 25% duty cycle. Waitcnt is used to align the second signal to the first, the current offset value aligns the second signal so that it's high period·spans the rising edge of the first signal. When run, the slave's·LED lights up. Setting offset to 21 places the second signal's high period to span the falling edge of the first signal, with this offset the LED remains off. Therefore ina is sampled on the rising edge of the clock.

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Paul Baker
Propeller Applications Engineer

Parallax, Inc.

Rayman

Thanks. That helps a lot.