Well that "other" companies chip not only has 4 threads at 100MIPS with deterministic timing on one core but also currently up to 4 cores. So a lot can be done in parallel. Somewhat Prop like ideas but instead of shared HUB ram some amazingly fast communication channels between cores.
Now I can see myself writing another 8080 emulator for the unmentioned device just as another assembly language challenge....
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
All my FPGA searching for a cheap intro kits (last 2 months) revealed the Xilinx kits were much cheaper than the ALtera. Verilog and VHDL are supported by both chips (software free for both).
Some other cheap Xilinx kits were here http://digilentinc.com/
Note the BASYS for US$59
The Nexys for US$99 has RAM
Both use the Spartan 3E
A Spartan 3AN has internal flash but I haven't seen a cheap kit yet.
As soon as I have finished my ClusoDebugger windows interface I am going to try and emulate a prop on the FPGA. Thanks to nutson for his great info. I got heavily distracted over the weekend, so will probably do a little of both from now on. Then all I will have to do is get both the Prop and FPGA boards talking together
One of the not considered points is power consumption. If you do not care... an FPGA can be a good idea. An XMOS XS-1-G4 eats around 1W @ 400 MHz; the unused cores can be powered down to save some 200 mW per core. FPGAs eat that much and more, while the propeller has great power/performance ratio, easy power supply requirements, and easier setup, and nicer packaging. It goes down to what you want. Proof of concept does not care about most of these details.
If you were to replicate the COG's instruction set, may be "upgrading it" to support larger memories would be a good idea. 512 registers are useful, but without a LMM-kernel or interpreted language they are somewhat crippled. Maybe extending the memory to 4 Klongs or something like that would improve many things.
On the xmos they implemented loads of interesting stuff directly in hardware. The channels are easy to use, you write one one end, you read on the other. That we need in the propeller (I think it was proposed to Chip). Clocked ports are also useful (something we could have modifying the video circuitry a bit to make it more general-purpose).
But in the end, they serve different purposes.
@heater: I'm working in a text vga driver for the xmos that is going to be out soon and a ps/2 interface (I already soldered the connector and had a look at the protocol and all), maybe that can serve you for your cp/m. Did you see the color driver ?
I have the Spartan 3E starter kit from Digilent, it is very good, well worth the money.
I would be willing to help with testing or debugging if you need any, if you go down the Spartan route.
I like the idea of emulating a Prop in hardware but we have to be careful here that it doesn't affect the Propeller itself if it was in the public domain for example.
I know if I was Parallax I wouldn't be too happy with that.
Just my two cents worth....
Regards,
Coley
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ PropGFX Forums - The home of the Hybrid Development System and PropGFX Lite
ARM jumped on some students who developed an ARM soft-core, it had to be withdrawn.
The Xilinx kits (especially those from Digilent) do tend to be cheaper than the Altera ones. They start at $99 for the Spartan-3 kit I've got, I paid the extra for the larger -400 part. The Altera tools are easier to use, and much less "clunky", though.
Leon
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
@Ale: There are many reasons why an FPGA will never replace a Prop:
1. Power consumption as you say
2. Cost
3. Size
4. Easy of use both physically and programming wise
5. Prop now has free cross platform tools
6. Pin drive current drive capability (I think)
7. Support from Parallax
etc etc
However for someone who wants to integrate a lot of peripheral high speed logic with a CPU into a single
chip perhaps a COG or entire Prop core might me an option worth considering.
Extending the COG space though requires a major change to the instruction set which does not seem worth
it as then you need to create your own assembler and compiler. Many of the soft CPUs created seem to only exist so as to make use of
existing tools and/or software and or know how.
For me a Verlog/VHDL prop would just be an educational amusement like the 8080 emulator.
I have suggested fast inter COG communication channels a few time here, as have others I think, never did get any feedback on that.
We should not discuss that "other" company here[noparse]:)[/noparse] but yes, interesting.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
@Coley and @Leon: I've been pondering the ethical and legal aspects of creating/publishing a Verilog/VHDL Prop for a long while now.
Legally, I have no idea about he details of trademark, copyright and patent law but it seems to me that:
If you don't actually call it a Propeller or worse a Parallax Propeller core I'd like to think there is no trademark problem.
As far as I can tell Parallax does not hold any patents on the Prop so there should be no patent problem. Not from Parallax anyway
and as far as I can tell Chip is not much in favour of patents.
There may be some copyright issue with the instruction set. At least with the published documentation but then one need not accompany
your VHDL source with any such documentation.
One could get into trade secret issues but if working from published information why should that be a problem.
There is definitely a problem with including the Spin interpreter without permission.
Ethically, well we don't want to put Parallax out of business but on reflection they might even like and benefit from a published Prop/COG core.
Think that's weird? Well firstly imitation is the sincerest form of flattery but more seriously if a Prop core turned up on OpenCores and elsewhere it
spreads the awareness of Parallax and the Prop. Makes the world see that we take them seriously enough to do that.
On the down side someone might take that core and start bashing out Prop clones in China. But I get the impression that is not so simple and by the time they've
done it Parallax are home dry with the Prop II anyway. Also even clones would have the effect of expanding the market awareness.
I love to here what Parallax and especially Chip have to say about all this. You see I'd quite like to have a go at a VHDL Prop or just a COG as a learning exercise but I don't want t o put the time in if I can't share the result and/or collaborate on creating it.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
Things like the instruction set are copyright. There has recently been a Supreme Court ruling in the USA about software patents and the law has been turned upside-down, which will cause companies like Microsoft lots of problems.
Leon
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
This where we can get into a tediously long debate about IP law[noparse]:)[/noparse]
For example why/how should an instruction set be copyrightable? That is exactly the details of how to use the device you have just bought. It's like saying no one can build a machine with the same operating knobs, switches and leavers as some one else's machine. Applied generally that is going to make every ones life hell. Is this light switch up for ON or down or sideways? The instruction manual perhaps yes but not the actual interface.
I've always thought software patents are just plain dumb. Copyright on your source code perhaps OK but not patents on some algorithm, seems like patenting mathematics to me. As for all these modern day business method patents well really....
And why should I be branded a pirate for making myself a copy some music that I can't buy anywhere because it been out of print for decades, whose "owners" will not let me have it until decades after the originators death which by the way will be decades after mine also.
Grumble, grumble.....
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
Copyright applies to everything that is published, which presumably can apply to an instruction set. In the UK one doesn't even have to use a copyright symbol to get protection, anything written is automatically copyright.
IIRC, Intel claimed copyright on their 8080 and 8051 instruction sets, which is why Zilog had to use something different for the Z80, although many of the instructions did the same thing as those on the 8080.
Leon
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
You know I'm not sure that is true. If I publish a list of all the numbers and times of all the buses that go past my house am I infringing the copyright of the bus company on their time table ? There must be a point where mere statement of facts is not infringing on someone else's creative work. It's not as if I scanned their schedule or copied all the same style, fonts and formatting.
The Intel/Zilog case is interesting as for sure the Z80 instruction set is a derived work of the 8080 even if the implementation is radically different. But look what happened they used different mnemonics to describe them and all was well.
And what about all those thousands of programming books that necessarily have to describe the instructions of the machines they are talking about. Do they all pay royalties to Intel, Motorola etc? I doubt it.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
The timetable document you produce is your copyright, and someone else isn't allowed to print it and distribute it without your permission. I think that is where the confusion arises. I don't think that Intel could have upheld their copyright in the UK.
Leon
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
My understanding is that copyright protection on instruction sets is zero (or next to it - unless someone patents some very fancy instruction set encoding).
Also, as far as I'm aware, mnemonic protection has been relaxed significantly since the 80s. For example, back then Zilog renamed MOV to LD. However, I doubt you could claim protection on using ADD, SUB, MOV, DIV, MUL. Theyre all derived from their purpose. You may be able to claim protection if you named your ADD instruction ZIGGLE. But if you named your ADD instruction ZIGGLE then anyone cloning you may wish to doubt their sanity.
Of course, this is only discussing the legal side, not the ethical.
Just a quick update to show the project is alive. I have two versions running at the moment:
- a non pipelined version that takes 3 clocks / instruction, doing·150MHz / 50 MIPS
- a version with two pipeline stages that takes 2 clocks / instruction, performing 160MHZ / 80 MIPS.
The instruction set now includes all·jumps and·instruction modification. A sample test program is attached.
(OT) I ported (read compiled) the Z80 emulator written by M de Kogel (used early by M.A.M.E) and I'm getting sort of 1 to 2 MIPS with 1 core. The memory is in another core and one channel is used to read it. An assembler version may get a guesstimate of 4 MIPS for the slowest instructions.
The Propeller Cog looks to be one of the easier architectures to emulate / replicate in FPGA or other silicon. Getting it working cycle perfect, exact emulation and at high speed are probably technical challenges limited by ability. Mixing in Hub Memory, Locks and Video Hardware is perhaps a bit more challenging but not impossible.
ARM probably get upset at free soft cores because that is their business, they don't sell hardware. Others get panicked by any potential threat to their revenues or IP base. Parallax on the other hand I expect would tend to be more impressed or be sending out job application forms than interested in unleashing the lawyers. It wouldn't surprise me if Chip were mainly interested in seeing how it were done and handing out info on how he did it in an enthusiastic compare-and-contrast manner.
Produce a full 8-Cog Propeller clone, cheaper or better and then you might become persona non grata.
I think this project is great. Really makes me want to get back to my studies of VHDL.
At this rate you will have a 64 I/O pin Propeller before Parallax [noparse]:)[/noparse]
Soon we can run a z80 emulation on a Prop on an FPGA....
@Ale: Yawn, I'm not impressed[noparse]:)[/noparse] My 8080 emulation has just hit half a MIP on the Prop. 4 COGS and PASM.
On your "chip that should remain nameless" you have 20 time the MIPS (400MIP core versus 20MIP COG) so I'm expecting 20 times the speed I get or 10MIPS of 8080 ops.
I don't know how ARM has a leg to stand on (forgive the pun). If one implements something that does what an ARM CPU does in a clean room way I don't see how copyrights come into it. Do they have a patent on something in there?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
Soon we can run a z80 emulation on a Prop on an FPGA....
I assume that was tongue in cheek.
Because why on earth would anyone do something like that? One can already implement a Z80 core on a FPGA without the nonsense of emulation on top of a specialized chip like the Prop.
Or better yet, why not go out and buy a 50mhz eZ80 for about $9.00 and bypass the Prop and FGPA altogether.
That said, the ARM folks probably do have some sort of IP going on that prevents them from being cloned. I remember a few years back some engineers designed a ARM clone for FPGA's and were slapped down by ARM lawyers, much the same way happened to folks who copied MIPS instruction set a little bit too well.
But for some reason, people who put out VHDL versions of the 8051, 6502, Z80 or even the 68000 are ignored. So go figure.
Why not emulate both CPUs in Parallel in same FPGA.
One for memory and one for I/O intensive work
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Nothing is impossible, there are only different degrees of difficulty. For every stupid question there is at least one intelligent answer. Don't guess - ask instead. If you don't ask you won't know. If your gonna construct something, make it·as simple as·possible yet as versatile as posible.
Er yeah, I was joking. BUT I do remember some years a go there was some sort of challenge going on as to who could get the most emulators/virtual machines stacked up on top of each other. Anything for kicks I guess.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
Quote: Creating a full specced COG is not my goal.·I want a simple controller to·perform I/O tasks,·example: an FPGA DDS synthesizer with the soft-CPU performing amplitude and frequency modulation.
There are too many features·missing at the moment to even dream·of a full COG or prop: correctly setting C and Z flags, conditional execution, hub memory that is byte/word/long adressable, WAITCNT etc etc. Next goal is to make·the DE-1 on board SRAM·256k16 accessable with RD/WRWORD instructions for multiple·clients (external control prop +·a number of·soft-COG's). And I need a better debug and test interface, and a better control interface and...... The DE-1 board has 72 free pins, I am using 12 for control and 8+ for outputs to the logic analyzer, so I have 52 pins free.
The only reason·for me to think of·a·full COG look-alike would be·to run the SPIN interpreter on it, and execute SPIN byte code. But if I do want to run a higher level language on the soft-COG, there may be better options. I feel it is feasible·(but outside my capabilities) to adapt the·Imagecraft C·compiler LMM kernel to my CPU (or adapt the CPU by adding extra instructions)·and run C·code on it.
Isn't it so that to get any kind of compiled code to run, indeed to write any kind of non-trival program in PASM requires conditional execution and hence Z and C flags?
I think it may be easier to continue adding COG features to your Verilog rather than to try and adapt any compiler to generate code for a "not a COG".
People would love you for it anyway.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
I'm using 1 thread, so only 100 MIPS are available, not 400 per thread. You are using 80 MIPS and getting .5 MIPS, I'm using C and getting 1 to 2 MIPS. It is not that bad. Usable for what I want. I already wrote a sort of working VT-100 emulator so I'm planning to boot CP/M soon, as soon as I get keyboard and SD car going. The text driver is already working, it consumes 2 threads!
Ale, I'm not knocking it, I'm just winding you up. These things are not easily comparable.
For example I'm not actually using 80 MIPS. The thing uses four COGs as that's the only way to get 8K bytes of fast PASM code into a Propeller. Only one COG is actually working at a time, on different parts of the 8080 opcode space. It would be more efficient if I could get all the code in one COG. I don't see any way to make use of the COGs parallelism in this case. So really I only have 20MIPS at my disposal. I did get 0.3 MIPS in the single COG version.
Yep, I don't care what they say about the efficient code generation of modern compilers I would expect an assembler version to be 4 or 8 times faster.
BTW. Did you spot that I already claimed to have created the worlds first single chip CP/M computer, including RAM and video out, on the Propeller? I'm sure someone else must have beaten us to it but have not found them yet.
Anyway, I hope one day to have time to check out the "chip that cannot be named here".
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
Hanging a Prop off an FPGA is pure genius... a bit of a niche, but a nice niche to be in. I can think of all kinds of applications and development purposes.
Exactly what you are doing with it at the moment doesn't really matter.
I would like to encourage you to publish the nuts of this somewhere... this would be a good place. Otherwise all you are doing is saying... "hey, look what I can do," which is fine but isn't terribly compelling.
Better to say "hey, look what you can do..."
I am not an engineer... so the acronyms constantly enlighten me. In this case Wikipedia lists 25 meanings for DDS... one of them is: digimon data squad (from season 5[noparse]:)[/noparse] On the other hand there is: direct digital synthesis, in which case I would wonder... can't you do that on a Prop?
I have the exact same FPGA... with a couple of cameras... everything works like it says on the shrink-wrap. It is just sitting there because I have too much to learn here before I can dream of going there. But if someone... such as you... would ease the path ... offer solutions that are meaningful from the Prop perspective... then the whole thing gets easier.
A product... any kind of product so long as it includes a Propeller and is completely documented... would be more than welcome.
If giving stuff away isn't your style and if you aren't into the product showcase mood... how about a subscription newsletter? You might only get one subscription, but I for one would like to know exactly what you are doing and how you are doing it.
Nico is using an Altera. I am using a Xilinx Spartan-3A (by Avnet $39). We are both using Verilog.
My emulation is taking care of all c & z options. Nothing running, just coding.
I think Chip said he was using an Altera Stratix III or IV.
@Chip:
Maybe Parallax could release a pcb with the Stratix on it with embedded PropII (The IP is protectable on these chips)??? What do you think Chip ???
You could release it quickly, with an update later as you add to the emulation - just an idea, but would be expensive for the fpga.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔ Links to other interesting threads:
The compiler is quite good at optimizing, so code is pretty tight. There are only 12 registers for general use and 4 can be used to pass parameters. What it lacks are flags, there are none. What it has instead are comparsion instructions that leave the result in a register, later 2 jump instructions (branch if true (!0) and branch if false (0)) are used. That clogs a register but well you cannot have everything. I miss: ANDN, flags (sometimes), and/or/xor with a literal (you have to use register). That in the propeller registers and memory positions are the same is quite neat but I really think I would have gone with a little less flexibility and a bit more COG memory, something like making implicit to write result and less flags combinations to gain the extra 2 bits, that it is just me .
I know all COGS are not running at the same time, but they are also not available for something else. Of course you cannot compare, they are different. When the PropII arrives things are going to get more even. I think (he) should increase the COG's memory it is not my decision.
@ heater: I will need to implement conditional execution, right.·Let me rephrase my C related statements: I think I can make a pretty·fast LMM execution engine. And I would be glad·to do something for the propeller community, it has given me so much already. If somebody·comes up with·a good idea how to use this soft-COG, I will actively support it.
@ rjo_ : My design is open and free,·drop me a PM with an E-mail adres and I will send the files, or a download link. Cluso already has an·earlier design. You have a DE-1 board? I will include instructions on hooking up a propeller to the DE-1, and downloading and executing programs into the soft_COG.··I am unsure how to publish design data and for what public. Forum members·that want to learn Verilog? I·started with Verilog a year ago, and have just scratched the surface of·all Quartus features (recently discovered that the barrel shifter and rotater account for almost half of·the·logic blocks in my design).·The one-eyed leading the blind?
For me the·role of this·embedded CPU will be·to·get fast (50MIPS+) and wide (32+ bit)·access to all the DE-1 board resources (memories, VGA, sound etc) and the external peripherals I plan on·hooking up (fast A/D·and D/A), and·to move·data around in the FPGA while doing·preprocessing. Example: get data from A/D FIFO input buffer, normalize, filter, and store into VGA memory for display.·Target is a distant vision of a super duper test and measurement system with multichannel DSO function, logic analyzer, AWG·(Arbitrary Waveform generator).
@Hippy: the propeller instruction set is very easy. All bit fields·have the same function in all instructions,·especially bit 23 "result written" is very handy in harware design.
@Cluso: Ken Gracey inquired in the PropII thread for interest in a·FPGA prototype to start early product development, but indicated·a hefty pricetag (4 digits). StratixIII prototype boards carry that kind of price.
nutson, If I understand you correctly by "make a pretty fast LMM execution engine" you have a pretty radical idea.
I interpret this as meaning that: One does not create a full up COG in Verilog which uses COG instructions in an LMM kernel to fetch LMM instructions and execute them, normal LMM style. Rather one creates the LMM kernel (a virtual machine) as a real machine in the FPGA.
That is you want to create a CPU core that executes the LMM output of ImageCraft C directly without the need for an LMM kernel loop of COG instructions.
Am I understanding you correctly ?
ImageCraft would love you for that, you would be executing the output of their Propeller compiler at 50MIPS rather than the 5 or whatever they get now using the LMM interpretter kernel.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
Comments
Now I can see myself writing another 8080 emulator for the unmentioned device just as another assembly language challenge....
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
Some other cheap Xilinx kits were here http://digilentinc.com/
Note the BASYS for US$59
The Nexys for US$99 has RAM
Both use the Spartan 3E
A Spartan 3AN has internal flash but I haven't seen a cheap kit yet.
As soon as I have finished my ClusoDebugger windows interface I am going to try and emulate a prop on the FPGA. Thanks to nutson for his great info. I got heavily distracted over the weekend, so will probably do a little of both from now on. Then all I will have to do is get both the Prop and FPGA boards talking together
If you were to replicate the COG's instruction set, may be "upgrading it" to support larger memories would be a good idea. 512 registers are useful, but without a LMM-kernel or interpreted language they are somewhat crippled. Maybe extending the memory to 4 Klongs or something like that would improve many things.
On the xmos they implemented loads of interesting stuff directly in hardware. The channels are easy to use, you write one one end, you read on the other. That we need in the propeller (I think it was proposed to Chip). Clocked ports are also useful (something we could have modifying the video circuitry a bit to make it more general-purpose).
But in the end, they serve different purposes.
@heater: I'm working in a text vga driver for the xmos that is going to be out soon and a ps/2 interface (I already soldered the connector and had a look at the protocol and all), maybe that can serve you for your cp/m. Did you see the color driver ?
I have the Spartan 3E starter kit from Digilent, it is very good, well worth the money.
I would be willing to help with testing or debugging if you need any, if you go down the Spartan route.
I like the idea of emulating a Prop in hardware but we have to be careful here that it doesn't affect the Propeller itself if it was in the public domain for example.
I know if I was Parallax I wouldn't be too happy with that.
Just my two cents worth....
Regards,
Coley
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
PropGFX Forums - The home of the Hybrid Development System and PropGFX Lite
The Xilinx kits (especially those from Digilent) do tend to be cheaper than the Altera ones. They start at $99 for the Spartan-3 kit I've got, I paid the extra for the larger -400 part. The Altera tools are easier to use, and much less "clunky", though.
Leon
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
1. Power consumption as you say
2. Cost
3. Size
4. Easy of use both physically and programming wise
5. Prop now has free cross platform tools
6. Pin drive current drive capability (I think)
7. Support from Parallax
etc etc
However for someone who wants to integrate a lot of peripheral high speed logic with a CPU into a single
chip perhaps a COG or entire Prop core might me an option worth considering.
Extending the COG space though requires a major change to the instruction set which does not seem worth
it as then you need to create your own assembler and compiler. Many of the soft CPUs created seem to only exist so as to make use of
existing tools and/or software and or know how.
For me a Verlog/VHDL prop would just be an educational amusement like the 8080 emulator.
I have suggested fast inter COG communication channels a few time here, as have others I think, never did get any feedback on that.
We should not discuss that "other" company here[noparse]:)[/noparse] but yes, interesting.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
Legally, I have no idea about he details of trademark, copyright and patent law but it seems to me that:
If you don't actually call it a Propeller or worse a Parallax Propeller core I'd like to think there is no trademark problem.
As far as I can tell Parallax does not hold any patents on the Prop so there should be no patent problem. Not from Parallax anyway
and as far as I can tell Chip is not much in favour of patents.
There may be some copyright issue with the instruction set. At least with the published documentation but then one need not accompany
your VHDL source with any such documentation.
One could get into trade secret issues but if working from published information why should that be a problem.
There is definitely a problem with including the Spin interpreter without permission.
Ethically, well we don't want to put Parallax out of business but on reflection they might even like and benefit from a published Prop/COG core.
Think that's weird? Well firstly imitation is the sincerest form of flattery but more seriously if a Prop core turned up on OpenCores and elsewhere it
spreads the awareness of Parallax and the Prop. Makes the world see that we take them seriously enough to do that.
On the down side someone might take that core and start bashing out Prop clones in China. But I get the impression that is not so simple and by the time they've
done it Parallax are home dry with the Prop II anyway. Also even clones would have the effect of expanding the market awareness.
I love to here what Parallax and especially Chip have to say about all this. You see I'd quite like to have a go at a VHDL Prop or just a COG as a learning exercise but I don't want t o put the time in if I can't share the result and/or collaborate on creating it.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
Post Edited (heater) : 11/10/2008 1:16:17 PM GMT
Leon
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
For example why/how should an instruction set be copyrightable? That is exactly the details of how to use the device you have just bought. It's like saying no one can build a machine with the same operating knobs, switches and leavers as some one else's machine. Applied generally that is going to make every ones life hell. Is this light switch up for ON or down or sideways? The instruction manual perhaps yes but not the actual interface.
I've always thought software patents are just plain dumb. Copyright on your source code perhaps OK but not patents on some algorithm, seems like patenting mathematics to me. As for all these modern day business method patents well really....
And why should I be branded a pirate for making myself a copy some music that I can't buy anywhere because it been out of print for decades, whose "owners" will not let me have it until decades after the originators death which by the way will be decades after mine also.
Grumble, grumble.....
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
IIRC, Intel claimed copyright on their 8080 and 8051 instruction sets, which is why Zilog had to use something different for the Z80, although many of the instructions did the same thing as those on the 8080.
Leon
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
The Intel/Zilog case is interesting as for sure the Z80 instruction set is a derived work of the 8080 even if the implementation is radically different. But look what happened they used different mnemonics to describe them and all was well.
And what about all those thousands of programming books that necessarily have to describe the instructions of the machines they are talking about. Do they all pay royalties to Intel, Motorola etc? I doubt it.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
Leon
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Amateur radio callsign: G1HSM
Suzuki SV1000S motorcycle
Also, as far as I'm aware, mnemonic protection has been relaxed significantly since the 80s. For example, back then Zilog renamed MOV to LD. However, I doubt you could claim protection on using ADD, SUB, MOV, DIV, MUL. Theyre all derived from their purpose. You may be able to claim protection if you named your ADD instruction ZIGGLE. But if you named your ADD instruction ZIGGLE then anyone cloning you may wish to doubt their sanity.
Of course, this is only discussing the legal side, not the ethical.
- a non pipelined version that takes 3 clocks / instruction, doing·150MHz / 50 MIPS
- a version with two pipeline stages that takes 2 clocks / instruction, performing 160MHZ / 80 MIPS.
The instruction set now includes all·jumps and·instruction modification. A sample test program is attached.
Nico Hattink
Now for the remainder of the instruction set. Did I send you the code for the logical instructions (shifts/rotates and and/or/xors) ?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps (SixBladeProp)
· Prop Tools under Development or Completed (Index)
· Emulators (Micros eg Altair, and Terminals eg VT100) - index
· Search the Propeller forums (via Google)
My cruising website is: ·www.bluemagic.biz
(OT) I ported (read compiled) the Z80 emulator written by M de Kogel (used early by M.A.M.E) and I'm getting sort of 1 to 2 MIPS with 1 core. The memory is in another core and one channel is used to read it. An assembler version may get a guesstimate of 4 MIPS for the slowest instructions.
ARM probably get upset at free soft cores because that is their business, they don't sell hardware. Others get panicked by any potential threat to their revenues or IP base. Parallax on the other hand I expect would tend to be more impressed or be sending out job application forms than interested in unleashing the lawyers. It wouldn't surprise me if Chip were mainly interested in seeing how it were done and handing out info on how he did it in an enthusiastic compare-and-contrast manner.
Produce a full 8-Cog Propeller clone, cheaper or better and then you might become persona non grata.
At this rate you will have a 64 I/O pin Propeller before Parallax [noparse]:)[/noparse]
Soon we can run a z80 emulation on a Prop on an FPGA....
@Ale: Yawn, I'm not impressed[noparse]:)[/noparse] My 8080 emulation has just hit half a MIP on the Prop. 4 COGS and PASM.
On your "chip that should remain nameless" you have 20 time the MIPS (400MIP core versus 20MIP COG) so I'm expecting 20 times the speed I get or 10MIPS of 8080 ops.
I don't know how ARM has a leg to stand on (forgive the pun). If one implements something that does what an ARM CPU does in a clean room way I don't see how copyrights come into it. Do they have a patent on something in there?
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
I assume that was tongue in cheek.
Because why on earth would anyone do something like that? One can already implement a Z80 core on a FPGA without the nonsense of emulation on top of a specialized chip like the Prop.
Or better yet, why not go out and buy a 50mhz eZ80 for about $9.00 and bypass the Prop and FGPA altogether.
That said, the ARM folks probably do have some sort of IP going on that prevents them from being cloned. I remember a few years back some engineers designed a ARM clone for FPGA's and were slapped down by ARM lawyers, much the same way happened to folks who copied MIPS instruction set a little bit too well.
But for some reason, people who put out VHDL versions of the 8051, 6502, Z80 or even the 68000 are ignored. So go figure.
Why not emulate both CPUs in Parallel in same FPGA.
One for memory and one for I/O intensive work
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Nothing is impossible, there are only different degrees of difficulty.
For every stupid question there is at least one intelligent answer.
Don't guess - ask instead.
If you don't ask you won't know.
If your gonna construct something, make it·as simple as·possible yet as versatile as posible.
Sapieha
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
There are too many features·missing at the moment to even dream·of a full COG or prop: correctly setting C and Z flags, conditional execution, hub memory that is byte/word/long adressable, WAITCNT etc etc. Next goal is to make·the DE-1 on board SRAM·256k16 accessable with RD/WRWORD instructions for multiple·clients (external control prop +·a number of·soft-COG's). And I need a better debug and test interface, and a better control interface and...... The DE-1 board has 72 free pins, I am using 12 for control and 8+ for outputs to the logic analyzer, so I have 52 pins free.
The only reason·for me to think of·a·full COG look-alike would be·to run the SPIN interpreter on it, and execute SPIN byte code. But if I do want to run a higher level language on the soft-COG, there may be better options. I feel it is feasible·(but outside my capabilities) to adapt the·Imagecraft C·compiler LMM kernel to my CPU (or adapt the CPU by adding extra instructions)·and run C·code on it.
Nico Hattink
I think it may be easier to continue adding COG features to your Verilog rather than to try and adapt any compiler to generate code for a "not a COG".
People would love you for it anyway.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
I'm using 1 thread, so only 100 MIPS are available, not 400 per thread. You are using 80 MIPS and getting .5 MIPS, I'm using C and getting 1 to 2 MIPS. It is not that bad. Usable for what I want. I already wrote a sort of working VT-100 emulator so I'm planning to boot CP/M soon, as soon as I get keyboard and SD car going. The text driver is already working, it consumes 2 threads!
For example I'm not actually using 80 MIPS. The thing uses four COGs as that's the only way to get 8K bytes of fast PASM code into a Propeller. Only one COG is actually working at a time, on different parts of the 8080 opcode space. It would be more efficient if I could get all the code in one COG. I don't see any way to make use of the COGs parallelism in this case. So really I only have 20MIPS at my disposal. I did get 0.3 MIPS in the single COG version.
Yep, I don't care what they say about the efficient code generation of modern compilers I would expect an assembler version to be 4 or 8 times faster.
BTW. Did you spot that I already claimed to have created the worlds first single chip CP/M computer, including RAM and video out, on the Propeller? I'm sure someone else must have beaten us to it but have not found them yet.
Anyway, I hope one day to have time to check out the "chip that cannot be named here".
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.
Hanging a Prop off an FPGA is pure genius... a bit of a niche, but a nice niche to be in. I can think of all kinds of applications and development purposes.
Exactly what you are doing with it at the moment doesn't really matter.
I would like to encourage you to publish the nuts of this somewhere... this would be a good place. Otherwise all you are doing is saying... "hey, look what I can do," which is fine but isn't terribly compelling.
Better to say "hey, look what you can do..."
I am not an engineer... so the acronyms constantly enlighten me. In this case Wikipedia lists 25 meanings for DDS... one of them is: digimon data squad (from season 5[noparse]:)[/noparse] On the other hand there is: direct digital synthesis, in which case I would wonder... can't you do that on a Prop?
I have the exact same FPGA... with a couple of cameras... everything works like it says on the shrink-wrap. It is just sitting there because I have too much to learn here before I can dream of going there. But if someone... such as you... would ease the path ... offer solutions that are meaningful from the Prop perspective... then the whole thing gets easier.
A product... any kind of product so long as it includes a Propeller and is completely documented... would be more than welcome.
If giving stuff away isn't your style and if you aren't into the product showcase mood... how about a subscription newsletter? You might only get one subscription, but I for one would like to know exactly what you are doing and how you are doing it.
Just a thought.
Rich
My emulation is taking care of all c & z options. Nothing running, just coding.
I think Chip said he was using an Altera Stratix III or IV.
@Chip:
Maybe Parallax could release a pcb with the Stratix on it with embedded PropII (The IP is protectable on these chips)??? What do you think Chip ???
You could release it quickly, with an update later as you add to the emulation - just an idea, but would be expensive for the fpga.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
Links to other interesting threads:
· Home of the MultiBladeProps (SixBladeProp)
· Prop Tools under Development or Completed (Index)
· Emulators (Micros eg Altair, and Terminals eg VT100) - index
· Search the Propeller forums (via Google)
My cruising website is: ·www.bluemagic.biz
Post Edited (Cluso99) : 2/9/2009 4:45:01 AM GMT
I know all COGS are not running at the same time, but they are also not available for something else. Of course you cannot compare, they are different. When the PropII arrives things are going to get more even. I think (he) should increase the COG's memory it is not my decision.
@ rjo_ : My design is open and free,·drop me a PM with an E-mail adres and I will send the files, or a download link. Cluso already has an·earlier design. You have a DE-1 board? I will include instructions on hooking up a propeller to the DE-1, and downloading and executing programs into the soft_COG.··I am unsure how to publish design data and for what public. Forum members·that want to learn Verilog? I·started with Verilog a year ago, and have just scratched the surface of·all Quartus features (recently discovered that the barrel shifter and rotater account for almost half of·the·logic blocks in my design).·The one-eyed leading the blind?
For me the·role of this·embedded CPU will be·to·get fast (50MIPS+) and wide (32+ bit)·access to all the DE-1 board resources (memories, VGA, sound etc) and the external peripherals I plan on·hooking up (fast A/D·and D/A), and·to move·data around in the FPGA while doing·preprocessing. Example: get data from A/D FIFO input buffer, normalize, filter, and store into VGA memory for display.·Target is a distant vision of a super duper test and measurement system with multichannel DSO function, logic analyzer, AWG·(Arbitrary Waveform generator).
@Hippy: the propeller instruction set is very easy. All bit fields·have the same function in all instructions,·especially bit 23 "result written" is very handy in harware design.
@Cluso: Ken Gracey inquired in the PropII thread for interest in a·FPGA prototype to start early product development, but indicated·a hefty pricetag (4 digits). StratixIII prototype boards carry that kind of price.
Regards, Nico Hattink
I interpret this as meaning that: One does not create a full up COG in Verilog which uses COG instructions in an LMM kernel to fetch LMM instructions and execute them, normal LMM style. Rather one creates the LMM kernel (a virtual machine) as a real machine in the FPGA.
That is you want to create a CPU core that executes the LMM output of ImageCraft C directly without the need for an LMM kernel loop of COG instructions.
Am I understanding you correctly ?
ImageCraft would love you for that, you would be executing the output of their Propeller compiler at 50MIPS rather than the 5 or whatever they get now using the LMM interpretter kernel.
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
For me, the past is not over yet.