CTRA PLL control

krazyideas

Hello

I am useing the CTRA mode %11010 to mesure pulse and I want to run the PLL at 128MHz.
I read this out of link talking about the counters A and B

I don't know how to change the range of the input Clock located in the counter to set it to 8MHz????
Do you do that by seting the system clock or what?
Thanks

A PLL is designed to work over a range of frequencies. The range for the input clock on the PLL
located within each counter is 4 to 8MHz, which results in an output range of 64 to 128 MHz.
Frequencies as low as 500 kHz can be output to APIN given the range of output divisions available
from the PLL. Therefore, any frequency from 500 kHz to 128 MHz can be generated using the PLL

counter modes.

Ken Peterson

Read AN001 - Propeller Counters available on the Propeller download page.· In counter mode %11010, the counter will count at the rate of the system clock whenever the input is high.· If you want to use the PLL, you need a different counter mode.

What are you trying to do with it anyway?

This question brings up a question in my own mind that someone else may be able to answer:· What is the difference between the following counter modes:

%01000 (POS Detector)·and %11010 (Logic A)
%01100 (NEG Detector) and %10101 (Logic !A)

·

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·"I have always wished that my computer would be as easy to use as my telephone.· My wish has come true.· I no longer know how to use my telephone."

- Bjarne Stroustrup

Post Edited (Ken Peterson) : 11/5/2008 1:33:27 PM GMT

Cluso99

I think you will find 128MHz exceeds the Props capabilities. I think Hippy uses the fastest xtal of 7.3xxMHz and PLL16. I think propgfx maybe using a 10MHz xtal and PLLx8. Hippy, you there?

Beau Schwabe

Cluso99,

The PLL that krazyideas is referring to are the CTRA and CTRB of each cog. These PLL's can generate signals from DC to 128MHz.

krazyideas,

Take a look at the "Synth" object located in the Library directory

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Beau Schwabe

IC Layout Engineer
Parallax, Inc.

Ken Peterson

Beau: That's a good point in case any reader is confused. The system clock is generated by a PLL off the crystal, and that PLL is limited to 80-100 MHz. The PLLs in the counters are fed from either the carry bit or bit 31 of the PHSA or PHSB registers and these PLLs can go up to 128MHz. If you want 128MHz on a counter PLL, then you need to set one of the counters in PLL mode and set FRQA (or FRQB) to the appropriate value so that bit 31 of PHSA (or PHSB) clocks at 8MHz. This value depends on what your system clock is. The PLL divider should be set for 16X. There are formulas in the AN001 document that decribe how to set it all up.

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·"I have always wished that my computer would be as easy to use as my telephone.· My wish has come true.· I no longer know how to use my telephone."

- Bjarne Stroustrup

Paul Baker

A further point of clarification, the system clock PLL's native oscillation must be between 64 and 128 MHz (this value is determined by multiplying the crystal frequency by 16), but you have the option of dividing this native frequency by 1, 2, 4, 8 or 16. This results in a resultant system clock frequency in the range of 4 to 128MHz, but the Propeller is spec'ed up to 80MHz, so the system clock range (using the PLL) is 4 to 80 MHz.

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Paul Baker
Propeller Applications Engineer

Parallax, Inc.