2nd Propeller Chip as additional ram?
Oldbitcollector (Jeff)
Posts: 8,091
The topic of figuring out how to get more ram resurfaces here about every two months.
Some of us have experimented with a few options to give more memory to the Propeller
some of the I2C stuff that can had, but it occurs to me that why don't we just use a 2nd
Propeller running some specialized spin code (something small) and use it's available
memory as additional for the 1st Propeller?
An expensive solution compared to others, but one that might be very easy to implement
using whatever method suits us.
Idea? or Dud?
OBC
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Some of us have experimented with a few options to give more memory to the Propeller
some of the I2C stuff that can had, but it occurs to me that why don't we just use a 2nd
Propeller running some specialized spin code (something small) and use it's available
memory as additional for the 1st Propeller?
An expensive solution compared to others, but one that might be very easy to implement
using whatever method suits us.
Idea? or Dud?
OBC
▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔▔
New to the Propeller?
Getting started with a Propeller Protoboard?
Check out: Introduction to the Proboard & Propeller Cookbook 1.4
Updates to the Cookbook are now posted to: Propeller.warrantyvoid.us
Got an SD card connected? - PropDOS
Comments
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I am 1011, so be surprised!
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Back in the dim dark ages, I did a 9 wire interface between 2 single chip micros to seperate 2 time critical tasks. I used an 8 bit (bi-directional bus) and 1 bit to indicate transfers/handshake. This method only allows 255 code transfers, else you require 2 transfer/handshake pins.
Remember though, you now have another 32 pins available, so you could also offload something to the second prop.
Xilinx have some dense serial eeproms for loading their FPGA's. Maybe you could add one of these also??
Now that there is a lot more understanding of the way the prop works (hub layout, etc), hub code could be laid out much better and any cog that needs loading could be loaded from flash directly (with the aid of a new simple loader). This would free up much of the hub ram. "Food for thought.."
John Abshier
with an 8bit bus and a some control bits. Just unsure how I want to address more than 255 bytes
of memory. Of course there is some trade off of I/O in this method, but returns in speed.
Could just go for wider bus.. [noparse]:)[/noparse]
OBC
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New to the Propeller?
Getting started with a Propeller Protoboard?
Check out: Introduction to the Proboard & Propeller Cookbook 1.4
Updates to the Cookbook are now posted to: Propeller.warrantyvoid.us
Got an SD card connected? - PropDOS
Edit: I forgot to mention that I use Beau's 4 bit method.
Post Edited (Ale) : 10/24/2008 10:49:37 AM GMT
http://forums.parallax.com/showthread.php?p=721563
I2C, SPI, 'RS232' and parallel bus interfaces can be used. It doesn't have to be RAM, it can be FIFO or LIFO, even ROM, single port or multi-ported. A single Propeller chip can support a mix of interfaces, shared or separate memory compartments.
I2C is perhaps the most useful because access objects exist and are easily written and tailored, clock-stretching can ensure the master runs as fast as it can but doesn't run too fast. It also allows the I2C RAM Propeller to also be used as an I/O expander, even a TV / Video driver, and it can have physical serial or parallel bus RAM added so an entire RAM module is 'abstracted via I2C'.
If one wants a genuinely unlimited erase cycle I2C RAM of large size using a Propeller this way isn't really that expensive. Using the techniques of multi-Propeller daisy-chain booting quite large I2C RAM can be built just by adding more Propeller chips although it will be slow to boot. The Propeller Mk II should allow 256Kx8 I2C RAM.
Using the master to boot the slave Propeller, addition of an extra Propeller requires little more than adding the extra Propeller chip.
SPI is an alternative to I2C and could allow MMC/SD Card emulation.
If I were looking at a parallel bus interface, I'd consider presenting the Propeller as an IDE HDD as a possibility, though that may require additional hardware interfacing for high-speed access.