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PLL counter mode — Parallax Forums

PLL counter mode

BeauHoundBeauHound Posts: 6
edited 2008-10-24 01:05 in Propeller 1
If use a cogs counter a and b in pll mode to output a 27mhz clock on separate pins are those to signals locked together ? (Phase and frequency)

Comments

  • Mike GreenMike Green Posts: 23,101
    edited 2008-10-24 00:43
    The signals are not locked. As far as I know, each counter has its own PLL.
  • BeauHoundBeauHound Posts: 6
    edited 2008-10-24 00:48
    thanks, mike

    what is the jitter rating for pll mode?
  • Paul BakerPaul Baker Posts: 6,351
    edited 2008-10-24 00:48
    The frequency will be the same, but thier phases may not be in alignment. It may be possible to get them within the jitter of the PLLs, but this would require careful assembly programming.

    I never measured the jitter of the PLLs when doing the datasheet, but Chip may know (at least the simulated jitter), I will ask him if he knows. I have a vague recollection of it being < 1 ns but I'm not positive.

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    Paul Baker
    Propeller Applications Engineer

    Parallax, Inc.

    Post Edited (Paul Baker (Parallax)) : 10/24/2008 12:53:43 AM GMT
  • RaymanRayman Posts: 15,058
    edited 2008-10-24 01:05
    You can look at the Hi-Res VGA driver code to see how to sync PLLs...· But, that's PLL's in different cogs...
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