assembly statement like if_z

ImmNek

Hello there,

My question is related to Propeller assembly conditions.


code Example:

asmDivision         cmp     dividend,       divisor      wc
        if_nc       sub     dividend,       divisor
        if_nc       jmp     #asmDivision 

In the first line the code compares two values, if the "dividend" is not lesser the "divisor" the two following lines of code will be executed.
If the "dividend" is less then the "divisor" the the two lines will not be executed. My question is, if the second and the third instruction takes together 8 clocks even if they will not be executed?

Thank you for your answers
Immanuel

Mike Green

Yes.

If you use conditional execution, the instructions behave as NOPs (no operation) if the condition is false. One NOP takes 4 clocks. Two NOPs take 8 clocks.

One reason to do this is that the timing of a routine can be easily made to be identical regardless of which instructions get executed. This can be done with JMPs, but is harder and more timing error prone.

Paul Baker

Yes each branch of the decision takes the same amount of time, 8 clock cycles. This behavior is actually desired because it helps maintain deterministic program, where no matter what decision path is taken a peice of code takes the same amount of time to execute. If you find yourself having a long string of if_nc statements (typically 3 or more instructions) that you dont want the if_c branch to execute as NOPs, simply insert if_c jmp #some_place in the program code.

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Paul Baker
Propeller Applications Engineer

Parallax, Inc.

Post Edited (Paul Baker (Parallax)) : 9/13/2008 7:43:18 PM GMT

ImmNek

Thanks a lot for your answers.
But when I have an instruction like rdlong that takes 7...22 clock cycles, how many cycles will take me this instruction if it will not be executed?
Mr Green said, that all instructions will become nop instruction if they will not be executed, is this right? Then I have different times for the same instruction.

hippy

I asked the same question about three weeks ago but it's already down on page 14 - things sure do fly by on this forum !

http://forums.parallax.com/showthread.php?p=744614

The definitive answer is on page 368 of the Propeller Manual 1.0; "When an instruction’s condition evaluates to FALSE , the instruction dynamically becomes a NOP , elapsing 4 clock cycles but affecting no flags or registers".

So a 'rdlong' etc will take 4 cycles if it's not executed.

If you want deterministic timing in both cases the best would be ...

        rdlong    tmp,adr
IF_Z    mov       reg,tmp

This looks good but I bet timing is completely screwed every which way ...

IF_Z    rdlong    reg,adr
IF_NZ   rdlong    tmp,adr          ' Read to ignored register

Post Edited (hippy) : 9/14/2008 3:38:13 AM GMT

ImmNek

Thanks a lot for your answer. Now it is totally clear for me.