Delay of 5 has 25ns with the propeller?

innoman

Hello,

I would like to write a drivers for vinculum VNC1L to use the mode parallel FIFO.
For the procedure of writing a delay of 5 has 25ns is asked for between falling edge of WR and the rising edge of TXE.
With CLK=80MHz, a instruction take 50ns.
How is it possible to get this delay?
I measured a gap of 20ns by using 2 cogs to generate 2 signs. Must I use this delay and use 2 cogs?

Phil Pilgrim (PhiPi)

The 25 ns timing (T5) is not a delay you have to provide. It's the delay from the Vinculum chip after your read strobe (RD#) ends before its RDF# output goes high. What this is saying is that you should wait at least 25 ns after RD# goes high before reading RDF#, to make sure you're seeing a valid level.

-Phil

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innoman

Thank's Phil, it would seem that I lack sleep