Hardware and software design question for VGA
Magister
Posts: 4
Hi, I am building a simple VGA controller board with 2 SX28 chips and 32x8K Ram. 1 of the SX is a master controller while the other SX is for vga timing generation. The resolution is 160x120 possible with 32x8k + character set. Well I think =]. Now the two problems I have are:
1: Both of the SX28 devices have control over the counters that drive the address bus of the Ram, which consists of 3 lines:
Clock Line,
Up/Down,
parallel Load
So when the vga timing SX device sends a interrupt to the master, then in the ISR the master releases the 3 lines by setting the RB 0,1,2 pins as input and
than later the vga SX sets the RB 0,1,2 as outputs to drive the lines before the active video (In Back porch before the active video starts") the display remains empty and
the bar i try to display does not show unless once the vga SX is done and dose not release the 3 lines to master because if it does they don't show.
if it back porch VGA SX sends interrupt to master to release ISR
SX Master sets RB 0,1,2 as Inputs
SX VGA sets RB 0,1,2 as Outputs
SX VGA Drives the lines for active video frame
SX VGA at The End of active video frame in the front porch sets RB 0,1,2 as inputs releasing the lines and sent a signal its done
SX Master does its own thing and waits for the Rb.7 to go low indicating that the active video is done and it can regain control of the 3 lines
this process repeats over and over but i does not work when the SX vga releases control of the lines than the display is just black even thou i set the address to
0 before video starts in the VGA SX so i know the address is right
Any Suggestions of how to make this work or alternative ? If more info schematic or code is needed no problem just let me know
2: The project is build on solder less experimenter board so maybe this the problem but on the display I can see Bars that are noise from the external clock that drives the SX28 I managed to reduce the noise but its still visible is there any trick or rule am not doing that right which makes the clock show on the display ?
Thank you Any help is appreciated, Sorry for such a long Post.
1: Both of the SX28 devices have control over the counters that drive the address bus of the Ram, which consists of 3 lines:
Clock Line,
Up/Down,
parallel Load
So when the vga timing SX device sends a interrupt to the master, then in the ISR the master releases the 3 lines by setting the RB 0,1,2 pins as input and
than later the vga SX sets the RB 0,1,2 as outputs to drive the lines before the active video (In Back porch before the active video starts") the display remains empty and
the bar i try to display does not show unless once the vga SX is done and dose not release the 3 lines to master because if it does they don't show.
if it back porch VGA SX sends interrupt to master to release ISR
SX Master sets RB 0,1,2 as Inputs
SX VGA sets RB 0,1,2 as Outputs
SX VGA Drives the lines for active video frame
SX VGA at The End of active video frame in the front porch sets RB 0,1,2 as inputs releasing the lines and sent a signal its done
SX Master does its own thing and waits for the Rb.7 to go low indicating that the active video is done and it can regain control of the 3 lines
this process repeats over and over but i does not work when the SX vga releases control of the lines than the display is just black even thou i set the address to
0 before video starts in the VGA SX so i know the address is right
Any Suggestions of how to make this work or alternative ? If more info schematic or code is needed no problem just let me know
2: The project is build on solder less experimenter board so maybe this the problem but on the display I can see Bars that are noise from the external clock that drives the SX28 I managed to reduce the noise but its still visible is there any trick or rule am not doing that right which makes the clock show on the display ?
Thank you Any help is appreciated, Sorry for such a long Post.
Comments
With the 16-bit timers and twice the code and ram, you might be able to do it all with one chip.
Bean.
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